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- Support inline asm 'w' constraint for 128-bit vector types.

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- Also support the 'q' NEON registers asm code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90894 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-12-08 23:06:22 +00:00
parent 32c9800a16
commit d831cda3e7
3 changed files with 19 additions and 0 deletions
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5
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -4021,6 +4021,8 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
return std::make_pair(0U, ARM::SPRRegisterClass);
if (VT == MVT::f64)
return std::make_pair(0U, ARM::DPRRegisterClass);
if (VT.getSizeInBits() == 128)
return std::make_pair(0U, ARM::QPRRegisterClass);
break;
}
}
@ -4059,6 +4061,9 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
ARM::D4, ARM::D5, ARM::D6, ARM::D7,
ARM::D8, ARM::D9, ARM::D10,ARM::D11,
ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
if (VT.getSizeInBits() == 128)
return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
break;
}

1
lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
View File

@ -1045,6 +1045,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
printNoHashImmediate(MI, OpNum);
return false;
case 'P': // Print a VFP double precision register.
case 'q': // Print a NEON quad precision register.
printOperand(MI, OpNum);
return false;
case 'Q':

13
test/CodeGen/ARM/inlineasm3.ll Normal file
View File

@ -0,0 +1,13 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
%struct.int32x4_t = type { <4 x i32> }
define arm_apcscc void @t() nounwind {
entry:
; CHECK: vmov.I64 q15, #0
; CHECK: vmov.32 d30[0], r0
; CHECK: vmov q0, q15
%tmp = alloca %struct.int32x4_t, align 16
call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind
ret void
}