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ARM: tblgen'erate more NEON two-operand aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155254 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
c827834d49
commit
d83c9ea7d1
@ -2494,6 +2494,7 @@ class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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(outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
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OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
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[(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
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let TwoOperandAliasConstraint = "$Vm = $Vd";
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let isCommutable = 0;
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}
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@ -2539,6 +2540,7 @@ class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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(outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
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OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
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[(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
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let TwoOperandAliasConstraint = "$Vm = $Vd";
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let isCommutable = 0;
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}
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@ -2885,6 +2887,7 @@ class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
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// Shift by immediate,
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// both double- and quad-register.
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let TwoOperandAliasConstraint = "$Vm = $Vd" in {
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class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
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Format f, InstrItinClass itin, Operand ImmTy,
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string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
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@ -2899,6 +2902,7 @@ class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
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(outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
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OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
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[(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
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}
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// Long shift by immediate.
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class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
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@ -3682,33 +3686,6 @@ multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
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def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
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OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
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// imm6 = xxxxxx
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// Aliases for two-operand forms (source and dest regs the same).
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "8 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v8i8"))
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DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "16 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v4i16"))
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DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "32 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v2i32"))
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DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "64 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v1i64"))
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DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "8 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v16i8"))
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QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "16 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v8i16"))
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QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "32 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v4i32"))
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QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
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def : NEONInstAlias<!strconcat(OpcodeStr, "${p}.", Dt, "64 $Vdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "v2i64"))
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QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
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}
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// Neon Shift-Accumulate vector operations,
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@ -5809,132 +5786,6 @@ def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Dm$lane",
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(VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
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VectorIndex32:$lane, pred:$p)>;
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// VSHL (immediate) two-operand aliases.
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def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
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(VSHLiv8i8 DPR:$Vdn, DPR:$Vdn, imm0_7:$imm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
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(VSHLiv4i16 DPR:$Vdn, DPR:$Vdn, imm0_15:$imm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
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(VSHLiv2i32 DPR:$Vdn, DPR:$Vdn, imm0_31:$imm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
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(VSHLiv1i64 DPR:$Vdn, DPR:$Vdn, imm0_63:$imm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
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(VSHLiv16i8 QPR:$Vdn, QPR:$Vdn, imm0_7:$imm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
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(VSHLiv8i16 QPR:$Vdn, QPR:$Vdn, imm0_15:$imm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
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(VSHLiv4i32 QPR:$Vdn, QPR:$Vdn, imm0_31:$imm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
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(VSHLiv2i64 QPR:$Vdn, QPR:$Vdn, imm0_63:$imm, pred:$p)>;
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// VSHL (register) two-operand aliases.
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def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
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(VSHLsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm",
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(VSHLsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm",
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(VSHLsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm",
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(VSHLsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm",
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(VSHLuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm",
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(VSHLuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm",
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(VSHLuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
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(VSHLuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
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(VSHLsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm",
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(VSHLsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm",
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(VSHLsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm",
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(VSHLsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm",
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(VSHLuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm",
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(VSHLuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm",
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(VSHLuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
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(VSHLuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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// VSHR (immediate) two-operand aliases.
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def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm",
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(VSHRsv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm",
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(VSHRsv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm",
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(VSHRsv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm",
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(VSHRsv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm",
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(VSHRsv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm",
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(VSHRsv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm",
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(VSHRsv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm",
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(VSHRsv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm",
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(VSHRuv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm",
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(VSHRuv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm",
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(VSHRuv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
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(VSHRuv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm",
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(VSHRuv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm",
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(VSHRuv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm",
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(VSHRuv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
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def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
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(VSHRuv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
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// VRSHL two-operand aliases.
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def : NEONInstAlias<"vrshl${p}.s8 $Vdn, $Vm",
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(VRSHLsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vrshl${p}.s16 $Vdn, $Vm",
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(VRSHLsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vrshl${p}.s32 $Vdn, $Vm",
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(VRSHLsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vrshl${p}.s64 $Vdn, $Vm",
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(VRSHLsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vrshl${p}.u8 $Vdn, $Vm",
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(VRSHLuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vrshl${p}.u16 $Vdn, $Vm",
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(VRSHLuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vrshl${p}.u32 $Vdn, $Vm",
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(VRSHLuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vrshl${p}.u64 $Vdn, $Vm",
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(VRSHLuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vrshl${p}.s8 $Vdn, $Vm",
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(VRSHLsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vrshl${p}.s16 $Vdn, $Vm",
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(VRSHLsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vrshl${p}.s32 $Vdn, $Vm",
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(VRSHLsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vrshl${p}.s64 $Vdn, $Vm",
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(VRSHLsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vrshl${p}.u8 $Vdn, $Vm",
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(VRSHLuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vrshl${p}.u16 $Vdn, $Vm",
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(VRSHLuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vrshl${p}.u32 $Vdn, $Vm",
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(VRSHLuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vrshl${p}.u64 $Vdn, $Vm",
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(VRSHLuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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// VLD1 single-lane pseudo-instructions. These need special handling for
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// the lane index that an InstAlias can't handle, so we use these instead.
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def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
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