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Don't enable the post-RA scheduler on x86 except at -O3. In its
current form, it is too expensive in compile time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90781 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -367,5 +367,5 @@ bool X86Subtarget::enablePostRAScheduler(
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RegClassVector& CriticalPathRCs) const {
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Mode = TargetSubtarget::ANTIDEP_CRITICAL;
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CriticalPathRCs.clear();
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return OptLevel >= CodeGenOpt::Default;
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return OptLevel >= CodeGenOpt::Aggressive;
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}
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@ -1,5 +1,5 @@
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; PR1075
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; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -O3 | FileCheck %s
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define float @foo(float %x) nounwind {
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%tmp1 = fmul float %x, 3.000000e+00
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s
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; RUN: llc < %s -mtriple=i386-apple-darwin10 -post-RA-scheduler=true | FileCheck %s
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; PR4958
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@ -1,4 +1,4 @@
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; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
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; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu -post-RA-scheduler=true | FileCheck %s
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; Currently, floating-point selects are lowered to CFG triangles.
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; This means that one side of the select is always unconditionally
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@ -1,5 +1,5 @@
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; Tests for SSE2 and below, without SSE3+.
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; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=pentium4 | FileCheck %s
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; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=pentium4 -O3 | FileCheck %s
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define void @t1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind {
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%tmp3 = load <2 x double>* %A, align 16
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@ -1,6 +1,6 @@
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; These are tests for SSE3 codegen. Yonah has SSE3 and earlier but not SSSE3+.
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; RUN: llc < %s -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9\
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; RUN: llc < %s -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9 -O3 \
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; RUN: | FileCheck %s --check-prefix=X64
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; Test for v8xi16 lowering where we extract the first element of the vector and
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@ -1,4 +1,4 @@
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false -post-RA-scheduler=true | FileCheck %s
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declare void @bar(i32)
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declare void @car(i32)
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@ -1,4 +1,4 @@
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; RUN: llc < %s -tailcallopt -march=x86-64 | FileCheck %s
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; RUN: llc < %s -tailcallopt -march=x86-64 -post-RA-scheduler=true | FileCheck %s
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; Check that lowered arguments on the stack do not overwrite each other.
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; Add %in1 %p1 to a different temporary register (%eax).
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@ -1,4 +1,4 @@
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; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
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; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -post-RA-scheduler=true | FileCheck %s
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; CHECK: paddw
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; CHECK: pextrw
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; CHECK: movd
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