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Expand bitcast support in fast isel to support bitcasts of non-constant values by emitting reg-reg copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55340 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -234,8 +234,36 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
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} else
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} else
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// TODO: Support vector and fp constants.
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// TODO: Support vector and fp constants.
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return I;
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return I;
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} else if (!isa<Constant>(I->getOperand(0))) {
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// Bitcasts of non-constant values become reg-reg copies.
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MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
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MVT DstVT = MVT::getMVT(I->getOperand(0)->getType());
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if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
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DstVT == MVT::Other || !DstVT.isSimple() ||
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!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
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// Unhandled type. Halt "fast" selection and bail.
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return I;
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if (!TLI.isConvertLegal(SrcVT, DstVT))
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// Illegal conversion. Halt "fast" selection and bail.
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return I:
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// Otherwise, insert a register-to-register copy.
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TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
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TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
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unsigned Op0 = ValueMap[I->getOperand(0)];
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unsigned ResultReg = createResultReg(DstClass);
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if (Op0 == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Op0, DstClass, SrcClass);
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ValueMap[I] = ResultReg;
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break;
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} else
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} else
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// TODO: Support non-constant bitcasts.
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// Casting a non-integral constant?
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return I;
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return I;
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default:
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default:
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