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X86FastISel support for conditional branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55816 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -19,7 +19,7 @@
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#include "X86RegisterInfo.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "X86TargetMachine.h"
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#include "llvm/InstrTypes.h"
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#include "llvm/Instructions.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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@ -52,6 +52,10 @@ private:
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bool X86SelectStore(Instruction *I);
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bool X86SelectStore(Instruction *I);
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bool X86SelectCmp(Instruction *I);
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bool X86SelectCmp(Instruction *I);
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bool X86SelectZExt(Instruction *I);
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bool X86SelectBranch(Instruction *I);
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unsigned TargetSelectConstantPoolLoad(Constant *C, MachineConstantPool* MCP);
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unsigned TargetSelectConstantPoolLoad(Constant *C, MachineConstantPool* MCP);
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};
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};
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@ -388,6 +392,36 @@ bool X86FastISel::X86SelectCmp(Instruction *I) {
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return true;
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return true;
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}
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}
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bool X86FastISel::X86SelectZExt(Instruction *I) {
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// Special-case hack: The only i1 values we know how to produce currently
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// set the upper bits of an i8 value to zero.
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if (I->getType() == Type::Int8Ty &&
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I->getOperand(0)->getType() == Type::Int1Ty) {
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unsigned ResultReg = getRegForValue(I->getOperand(0));
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UpdateValueMap(I, ResultReg);
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return true;
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}
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return false;
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}
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bool X86FastISel::X86SelectBranch(Instruction *I) {
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BranchInst *BI = cast<BranchInst>(I);
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// Unconditional branches are selected by tablegen-generated code.
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unsigned OpReg = getRegForValue(BI->getCondition());
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MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
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MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
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BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
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BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
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BuildMI(MBB, TII.get(X86::JMP)).addMBB(FalseMBB);
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MBB->addSuccessor(TrueMBB);
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MBB->addSuccessor(FalseMBB);
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return true;
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}
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bool
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bool
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X86FastISel::TargetSelectInstruction(Instruction *I) {
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X86FastISel::TargetSelectInstruction(Instruction *I) {
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switch (I->getOpcode()) {
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switch (I->getOpcode()) {
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@ -399,6 +433,10 @@ X86FastISel::TargetSelectInstruction(Instruction *I) {
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case Instruction::ICmp:
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case Instruction::ICmp:
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case Instruction::FCmp:
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case Instruction::FCmp:
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return X86SelectCmp(I);
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return X86SelectCmp(I);
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case Instruction::ZExt:
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return X86SelectZExt(I);
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case Instruction::Br:
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return X86SelectBranch(I);
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}
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}
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return false;
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return false;
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