From d8e0c0438ab1ec86b2bd42da7a439caa7f0a61eb Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Thu, 9 Dec 2010 02:52:17 +0000 Subject: [PATCH] Really check that the bits that will become zero are actually already zero before eliminating the operation that zeros them. This fixes rdar://8739316. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121353 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../InstCombine/InstCombineShifts.cpp | 3 +-- .../InstCombine/2010-11-01-lshr-mask.ll | 26 ++++++++++++++++++- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/lib/Transforms/InstCombine/InstCombineShifts.cpp b/lib/Transforms/InstCombine/InstCombineShifts.cpp index e52f2013fe5..e3232a491b7 100644 --- a/lib/Transforms/InstCombine/InstCombineShifts.cpp +++ b/lib/Transforms/InstCombine/InstCombineShifts.cpp @@ -168,9 +168,8 @@ static bool CanEvaluateShifted(Value *V, unsigned NumBits, bool isLeftShift, // We can always turn lshr(c1)+shl(c2) -> lshr(c3)+and(c4), but it isn't // profitable unless we know the and'd out bits are already zero. if (CI->getZExtValue() > NumBits) { - unsigned LowBits = CI->getZExtValue() - NumBits; if (MaskedValueIsZero(I->getOperand(0), - APInt::getLowBitsSet(TypeWidth, LowBits) << NumBits)) + APInt::getLowBitsSet(TypeWidth, NumBits))) return true; } diff --git a/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll b/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll index d74c70e4f75..34b165bcbe7 100644 --- a/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll +++ b/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll @@ -1,6 +1,7 @@ ; RUN: opt -instcombine -S < %s | FileCheck %s -; +; +; CHECK: @main define i32 @main(i32 %argc) nounwind ssp { entry: %tmp3151 = trunc i32 %argc to i8 @@ -18,3 +19,26 @@ entry: ; CHECK: ret i32 ret i32 %tmp4086 } + +; rdar://8739316 +; CHECK: @foo +define i8 @foo(i8 %arg, i8 %arg1) nounwind { +bb: + %tmp = shl i8 %arg, 7 + %tmp2 = and i8 %arg1, 84 + %tmp3 = and i8 %arg1, -118 + %tmp4 = and i8 %arg1, 33 + %tmp5 = sub i8 -88, %tmp2 + %tmp6 = and i8 %tmp5, 84 + %tmp7 = or i8 %tmp4, %tmp6 + %tmp8 = xor i8 %tmp, %tmp3 + %tmp9 = or i8 %tmp7, %tmp8 + %tmp10 = lshr i8 %tmp8, 7 + %tmp11 = shl i8 %tmp10, 5 + +; CHECK: %0 = lshr i8 %tmp8, 2 +; CHECK: %tmp11 = and i8 %0, 32 + + %tmp12 = xor i8 %tmp11, %tmp9 + ret i8 %tmp12 +}