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Clarify the doxygen comment for AsmPrinter::EmitDwarfRegOpPiece and add

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default arguments to the function.

No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207372 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adrian Prantl 2014-04-27 18:50:45 +00:00
parent 3551384ae2
commit d8e141c0c1
2 changed files with 16 additions and 9 deletions
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13
include/llvm/CodeGen/AsmPrinter.h
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@ -430,14 +430,21 @@ namespace llvm {
/// encoding specified. /// encoding specified.
virtual unsigned getISAEncoding() { return 0; } virtual unsigned getISAEncoding() { return 0; }
/// \brief Emit a partial dwarf register operation. /// \brief Emit a partial DWARF register operation.
/// \param MLoc the register /// \param MLoc the register
/// \param PieceSizeInBits size and /// \param PieceSizeInBits size and
/// \param PieceOffsetBits offset of the piece in bits, if this is one /// \param PieceOffsetBits offset of the piece in bits, if this is one
/// piece of an aggregate value. /// piece of an aggregate value.
///
/// If size and offset is zero an operation for the entire
/// register is emitted: Some targets do not provide a DWARF
/// register number for every register. If this is the case, this
/// function will attempt to emit a DWARF register by emitting a
/// piece of a super-register or by piecing together multiple
/// subregisters that alias the register.
void EmitDwarfRegOpPiece(ByteStreamer &BS, const MachineLocation &MLoc, void EmitDwarfRegOpPiece(ByteStreamer &BS, const MachineLocation &MLoc,
unsigned PieceSize, unsigned PieceSize = 0,
unsigned PieceOffset) const; unsigned PieceOffset = 0) const;
/// EmitDwarfRegOp - Emit dwarf register operation. /// EmitDwarfRegOp - Emit dwarf register operation.
/// \param Indirect whether this is a register-indirect address /// \param Indirect whether this is a register-indirect address

12
lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
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@ -240,15 +240,15 @@ static void emitDwarfOpShr(ByteStreamer &Streamer,
Streamer.EmitInt8(dwarf::DW_OP_shr, "DW_OP_shr"); Streamer.EmitInt8(dwarf::DW_OP_shr, "DW_OP_shr");
} }
/// Some targets do not provide a DWARF register number for every // Some targets do not provide a DWARF register number for every
/// register. This function attempts to emit a DWARF register by // register. This function attempts to emit a DWARF register by
/// emitting a piece of a super-register or by piecing together // emitting a piece of a super-register or by piecing together
/// multiple subregisters that alias the register. // multiple subregisters that alias the register.
void AsmPrinter::EmitDwarfRegOpPiece(ByteStreamer &Streamer, void AsmPrinter::EmitDwarfRegOpPiece(ByteStreamer &Streamer,
const MachineLocation &MLoc, const MachineLocation &MLoc,
unsigned PieceSizeInBits, unsigned PieceSizeInBits,
unsigned PieceOffsetInBits) const { unsigned PieceOffsetInBits) const {
assert(!MLoc.isIndirect()); assert(MLoc.isReg() && "MLoc must be a register");
const TargetRegisterInfo *TRI = TM.getRegisterInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo();
int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false); int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
@ -346,7 +346,7 @@ void AsmPrinter::EmitDwarfRegOp(ByteStreamer &Streamer,
} }
// Attempt to find a valid super- or sub-register. // Attempt to find a valid super- or sub-register.
return EmitDwarfRegOpPiece(Streamer, MLoc, 0, 0); return EmitDwarfRegOpPiece(Streamer, MLoc);
} }
if (MLoc.isIndirect()) if (MLoc.isIndirect())