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Replace vfmaddxx213 instructions with their 231-type equivalents in accumulator
loops. Writing back to the accumulator (231-type) allows the coalescer to eliminate an extra copy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199933 91177308-0d34-0410-b5e6-96231b3b80d8
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Lang Hames
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@ -15963,6 +15963,81 @@ X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
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return MBB;
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}
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// Replace 213-type (isel default) FMA3 instructions with 231-type for
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// accumulator loops. Writing back to the accumulator allows the coalescer
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// to remove extra copies in the loop.
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MachineBasicBlock *
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X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
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MachineBasicBlock *MBB) const {
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MachineOperand &AddendOp = MI->getOperand(3);
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// Bail out early if the addend isn't a register - we can't switch these.
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if (!AddendOp.isReg())
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return MBB;
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MachineFunction &MF = *MBB->getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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// Check whether the addend is defined by a PHI:
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assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
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MachineInstr &AddendDef = *MRI.def_begin(AddendOp.getReg());
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if (!AddendDef.isPHI())
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return MBB;
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// Look for the following pattern:
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// loop:
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// %addend = phi [%entry, 0], [%loop, %result]
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// ...
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// %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
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// Replace with:
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// loop:
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// %addend = phi [%entry, 0], [%loop, %result]
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// ...
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// %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
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for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
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assert(AddendDef.getOperand(i).isReg());
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MachineOperand PHISrcOp = AddendDef.getOperand(i);
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MachineInstr &PHISrcInst = *MRI.def_begin(PHISrcOp.getReg());
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if (&PHISrcInst == MI) {
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// Found a matching instruction.
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unsigned NewFMAOpc = 0;
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switch (MI->getOpcode()) {
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case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
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case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
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case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
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case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
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case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
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case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
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case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
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case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
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case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
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case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
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case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
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case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
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case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
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case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
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case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
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case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
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default: llvm_unreachable("Unrecognized FMA variant.");
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}
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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MachineInstrBuilder MIB =
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BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
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.addOperand(MI->getOperand(0))
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.addOperand(MI->getOperand(3))
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.addOperand(MI->getOperand(2))
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.addOperand(MI->getOperand(1));
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MBB->insert(MachineBasicBlock::iterator(MI), MIB);
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MI->eraseFromParent();
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}
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}
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return MBB;
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}
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MachineBasicBlock *
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X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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@ -16194,6 +16269,32 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case TargetOpcode::STACKMAP:
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case TargetOpcode::PATCHPOINT:
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return emitPatchPoint(MI, BB);
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case X86::VFMADDPDr213r:
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case X86::VFMADDPSr213r:
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case X86::VFMADDSDr213r:
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case X86::VFMADDSSr213r:
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case X86::VFMSUBPDr213r:
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case X86::VFMSUBPSr213r:
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case X86::VFMSUBSDr213r:
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case X86::VFMSUBSSr213r:
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case X86::VFNMADDPDr213r:
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case X86::VFNMADDPSr213r:
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case X86::VFNMADDSDr213r:
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case X86::VFNMADDSSr213r:
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case X86::VFNMSUBPDr213r:
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case X86::VFNMSUBPSr213r:
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case X86::VFNMSUBSDr213r:
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case X86::VFNMSUBSSr213r:
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case X86::VFMADDPDr213rY:
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case X86::VFMADDPSr213rY:
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case X86::VFMSUBPDr213rY:
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case X86::VFMSUBPSr213rY:
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case X86::VFNMADDPDr213rY:
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case X86::VFNMADDPSr213rY:
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case X86::VFNMSUBPDr213rY:
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case X86::VFNMSUBPSr213rY:
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return emitFMA3Instr(MI, BB);
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}
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}
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@ -972,6 +972,9 @@ namespace llvm {
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MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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/// Emit nodes that will be selected as "test Op0,Op0", or something
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/// equivalent, for use with the given x86 condition code.
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SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
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@ -20,7 +20,7 @@ multiclass fma3p_rm<bits<8> opc, string OpcodeStr,
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PatFrag MemFrag128, PatFrag MemFrag256,
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ValueType OpVT128, ValueType OpVT256,
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SDPatternOperator Op = null_frag> {
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let isCommutable = 1 in
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let isCommutable = 1, usesCustomInserter = 1 in
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def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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@ -36,7 +36,7 @@ multiclass fma3p_rm<bits<8> opc, string OpcodeStr,
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[(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
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(MemFrag128 addr:$src3))))]>;
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let isCommutable = 1 in
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let isCommutable = 1, usesCustomInserter = 1 in
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def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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@ -118,7 +118,7 @@ let Constraints = "$src1 = $dst" in {
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multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
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RegisterClass RC, ValueType OpVT, PatFrag mem_frag,
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SDPatternOperator OpNode = null_frag> {
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let isCommutable = 1 in
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let isCommutable = 1, usesCustomInserter = 1 in
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def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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@ -42,6 +42,21 @@ entry:
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ret float %call
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}
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; Test FMA3 variant selection
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; CHECK: fma3_select231:
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; CHECK: vfmadd231ss
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define float @fma3_select231(float %x, float %y, i32 %N) #0 {
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entry:
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br label %while.body
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while.body: ; preds = %while.body, %while.body
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%acc.01 = phi float [ 0.000000e+00, %entry ], [ %acc, %while.body ]
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%acc = tail call float @llvm.fma.f32(float %x, float %y, float %acc.01) nounwind readnone
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%b = fcmp ueq float %acc, 0.0
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br i1 %b, label %while.body, label %while.end
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while.end: ; preds = %while.body, %entry
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ret float %acc
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}
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declare float @llvm.fma.f32(float, float, float) nounwind readnone
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declare double @llvm.fma.f64(double, double, double) nounwind readnone
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declare x86_fp80 @llvm.fma.f80(x86_fp80, x86_fp80, x86_fp80) nounwind readnone
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