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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-25 00:29:20 +00:00
Reapply Eli's r127852 now that the pre-RA scheduler can spill EFLAGS.
(target-specific branchless method for double-width relational comparisons on x86) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128175 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -447,12 +447,13 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::SETCC , MVT::i8 , Custom);
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setOperationAction(ISD::SETCC , MVT::i16 , Custom);
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setOperationAction(ISD::SETCC , MVT::i32 , Custom);
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setOperationAction(ISD::SETCC , MVT::i64 , Custom);
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setOperationAction(ISD::SETCC , MVT::f32 , Custom);
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setOperationAction(ISD::SETCC , MVT::f64 , Custom);
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setOperationAction(ISD::SETCC , MVT::f80 , Custom);
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::SELECT , MVT::i64 , Custom);
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setOperationAction(ISD::SETCC , MVT::i64 , Custom);
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setOperationAction(ISD::SETCC , MVT::i128 , Custom);
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}
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setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
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@ -2853,7 +2854,7 @@ static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
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} else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
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// X < 0 -> X == 0, jump on sign.
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return X86::COND_S;
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} else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
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} else if (SetCCOpcode == ISD::SETLT && RHSC->isOne()) {
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// X < 1 -> X <= 0
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RHS = DAG.getConstant(0, RHS.getValueType());
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return X86::COND_LE;
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@ -7436,7 +7437,8 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
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// Lower (X & (1 << N)) == 0 to BT(X, N).
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// Lower ((X >>u N) & 1) != 0 to BT(X, N).
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// Lower ((X >>s N) & 1) != 0 to BT(X, N).
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if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
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if (isTypeLegal(Op0.getValueType()) &&
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Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
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Op1.getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(Op1)->isNullValue() &&
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(CC == ISD::SETEQ || CC == ISD::SETNE)) {
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@ -7448,7 +7450,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
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// Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
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// these.
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if (Op1.getOpcode() == ISD::Constant &&
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(cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
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(cast<ConstantSDNode>(Op1)->isOne() ||
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cast<ConstantSDNode>(Op1)->isNullValue()) &&
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(CC == ISD::SETEQ || CC == ISD::SETNE)) {
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@ -7471,6 +7473,73 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
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if (X86CC == X86::COND_INVALID)
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return SDValue();
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if ((!Subtarget->is64Bit() && Op0.getValueType() == MVT::i64) ||
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(Subtarget->is64Bit() && Op0.getValueType() == MVT::i128)) {
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switch (X86CC) {
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case X86::COND_E:
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case X86::COND_NE:
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case X86::COND_S:
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case X86::COND_NS:
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// Just use the generic lowering, which works well on x86.
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return SDValue();
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case X86::COND_B:
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case X86::COND_AE:
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case X86::COND_L:
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case X86::COND_GE:
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// Use SBB-based lowering.
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break;
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case X86::COND_A:
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// Use SBB-based lowering; commute so ZF isn't used.
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X86CC = X86::COND_B;
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std::swap(Op0, Op1);
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break;
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case X86::COND_BE:
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// Use SBB-based lowering; commute so ZF isn't used.
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X86CC = X86::COND_AE;
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std::swap(Op0, Op1);
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break;
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case X86::COND_G:
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// Use SBB-based lowering; commute so ZF isn't used.
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X86CC = X86::COND_L;
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std::swap(Op0, Op1);
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break;
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case X86::COND_LE:
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// Use SBB-based lowering; commute so ZF isn't used.
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X86CC = X86::COND_GE;
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std::swap(Op0, Op1);
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break;
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default:
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assert(0 && "Unexpected X86CC.");
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return SDValue();
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}
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MVT HalfType = getPointerTy();
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// FIXME: Refactor this code out to implement ISD::SADDO and friends.
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SDValue Op0Low = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfType,
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Op0, DAG.getIntPtrConstant(0));
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SDValue Op1Low = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfType,
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Op1, DAG.getIntPtrConstant(0));
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SDValue Op0High = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfType,
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Op0, DAG.getIntPtrConstant(1));
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SDValue Op1High = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfType,
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Op1, DAG.getIntPtrConstant(1));
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// Redirect some cases which will simplify to the generic expansion;
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// X86ISD::SUB and X86ISD::SBB are not optimized well at the moment.
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// FIXME: We really need to add DAGCombines for SUB/SBB/etc.
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if (Op1Low.getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(Op1Low)->isNullValue())
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return SDValue();
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if (Op0Low.getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(Op0Low)->isAllOnesValue())
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return SDValue();
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SDValue res1, res2;
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SDVTList VTList = DAG.getVTList(HalfType, MVT::i32);
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res1 = DAG.getNode(X86ISD::SUB, dl, VTList, Op0Low, Op1Low).getValue(1);
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res2 = DAG.getNode(X86ISD::SBB, dl, VTList, Op0High, Op1High,
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res1).getValue(1);
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return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
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DAG.getConstant(X86CC, MVT::i8), res2);
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}
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SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
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return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
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DAG.getConstant(X86CC, MVT::i8), EFLAGS);
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@ -1,18 +1,35 @@
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; RUN: llc < %s -march=x86 | grep cmp | count 1
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; RUN: llc < %s -march=x86 | grep shr | count 1
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; RUN: llc < %s -march=x86 | grep xor | count 1
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; RUN: llc < %s -march=x86 | FileCheck %s
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define i1 @t1(i64 %x) nounwind {
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%B = icmp slt i64 %x, 0
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ret i1 %B
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; General case
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define i1 @t1(i64 %x, i64 %y) nounwind {
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; CHECK: @t1
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; CHECK: subl
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; CHECK: sbbl
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; CHECK: setl %al
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%B = icmp slt i64 %x, %y
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ret i1 %B
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}
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; Some special cases
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define i1 @t2(i64 %x) nounwind {
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%tmp = icmp ult i64 %x, 4294967296
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ret i1 %tmp
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; CHECK: @t2
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; CHECK: shrl $31, %eax
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%B = icmp slt i64 %x, 0
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ret i1 %B
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}
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define i1 @t3(i32 %x) nounwind {
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%tmp = icmp ugt i32 %x, -1
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ret i1 %tmp
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define i1 @t3(i64 %x) nounwind {
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; CHECK: @t3
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; CHECX: cmpl $0
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; CHECX: sete %al
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%tmp = icmp ult i64 %x, 4294967296
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ret i1 %tmp
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}
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define i1 @t4(i64 %x) nounwind {
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; CHECK: @t4
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; CHECX: cmpl $0
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; CHECX: setne %al
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%tmp = icmp ugt i64 %x, 4294967295
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ret i1 %tmp
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}
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@ -39,7 +39,8 @@ entry:
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; 32: t3:
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; 32: cmpl $1
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; 32: sbbl
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; 32: cmpl
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; 32: subl
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; 32: sbbl
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; 32: xorl
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; 64: t3:
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