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Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162740 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3432,6 +3432,10 @@ bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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case X86::AVX_SET0:
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assert(HasAVX && "AVX not supported");
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return Expand2AddrUndef(MI, get(X86::VXORPSYrr));
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case X86::V_SETALLONES:
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return Expand2AddrUndef(MI, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
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case X86::AVX2_SETALLONES:
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return Expand2AddrUndef(MI, get(X86::VPCMPEQDYrr));
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case X86::TEST8ri_NOREX:
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MI->setDesc(get(X86::TEST8ri));
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return true;
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@ -3789,7 +3793,6 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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break;
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case X86::V_SET0:
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case X86::V_SETALLONES:
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case X86::AVX_SETALLONES:
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Alignment = 16;
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break;
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case X86::FsFLD0SD:
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@ -3825,7 +3828,6 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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switch (LoadMI->getOpcode()) {
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case X86::V_SET0:
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case X86::V_SETALLONES:
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case X86::AVX_SETALLONES:
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case X86::AVX2_SETALLONES:
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case X86::AVX_SET0:
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case X86::FsFLD0SD:
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@ -3864,8 +3866,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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else
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Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
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bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES ||
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Opc == X86::AVX2_SETALLONES);
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bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
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const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
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Constant::getNullValue(Ty);
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unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
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@ -436,19 +436,13 @@ def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
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// We set canFoldAsLoad because this can be converted to a constant-pool
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// load of an all-ones value if folding it would be beneficial.
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// FIXME: Change encoding to pseudo! This is blocked right now by the x86
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// JIT implementation, it does not expand the instructions below like
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// X86MCInstLower does.
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
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let Predicates = [HasAVX] in
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def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
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def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4i32 immAllOnesV))]>;
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isPseudo = 1 in {
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def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4i32 immAllOnesV))]>;
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let Predicates = [HasAVX2] in
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def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
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[(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
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def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
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[(set VR256:$dst, (v8i32 immAllOnesV))]>;
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}
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@ -377,9 +377,6 @@ ReSimplify:
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case X86::SETB_C64r: LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break;
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case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
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case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
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case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;
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case X86::AVX_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::VPCMPEQDrr); break;
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case X86::AVX2_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::VPCMPEQDYrr);break;
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case X86::MOV16r0:
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LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0
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