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https://github.com/c64scene-ar/llvm-6502.git
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DAG based isel call support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25103 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
941334f0b0
commit
d90eb7fb24
@ -410,6 +410,33 @@ SDOperand X86DAGToDAGISel::Select(SDOperand N) {
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return CodeGenMap[N] = CurDAG->getTargetNode(Opc, VT, Result);
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break;
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}
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case ISD::ConstantFP: {
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Opc = 0;
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if (X86ScalarSSE) {
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assert(cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0) &&
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"SSE only supports +0.0");
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Opc = (NVT == MVT::f32) ? X86::FLD0SS : X86::FLD0SD;
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}
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if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0) ||
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cast<ConstantFPSDNode>(N)->isExactlyValue(-0.0))
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Opc = X86::FpLD0;
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else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0) ||
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cast<ConstantFPSDNode>(N)->isExactlyValue(-1.0))
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Opc = X86::FpLD1;
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assert(Opc != 0 && "Unexpected constant!");
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SDOperand Result = CurDAG->getTargetNode(Opc, NVT);
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if (cast<ConstantFPSDNode>(N)->getValue() < 0.0 ||
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cast<ConstantFPSDNode>(N)->isExactlyValue(-0.0))
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Result = CurDAG->getTargetNode(X86::FpCHS, NVT, Result);
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CodeGenMap[N] = Result;
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return Result;
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}
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}
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return SelectCode(N);
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@ -457,38 +457,117 @@ X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
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RetVals.push_back(MVT::i32);
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break;
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}
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std::vector<SDOperand> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
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Ops.push_back(DAG.getConstant(0, getPointerTy()));
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SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
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RetVals, Ops);
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Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
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SDOperand ResultVal;
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switch (RetTyVT) {
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case MVT::isVoid: break;
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default:
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ResultVal = TheCall.getValue(1);
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
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break;
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case MVT::f32:
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// FIXME: we would really like to remember that this FP_ROUND operation is
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// okay to eliminate if we allow excess FP precision.
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ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
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break;
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case MVT::i64:
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ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
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TheCall.getValue(2));
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break;
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if (X86DAGIsel) {
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std::vector<MVT::ValueType> NodeTys;
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NodeTys.push_back(MVT::Other); // Returns a chain
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NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
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std::vector<SDOperand> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
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NodeTys, Ops);
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SDOperand InFlag = Chain.getValue(1);
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SDOperand RetVal;
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if (RetTyVT != MVT::isVoid) {
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switch (RetTyVT) {
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default: assert(0 && "Unknown value type to return!");
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case MVT::i1:
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case MVT::i8:
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RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
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Chain = RetVal.getValue(1);
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break;
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case MVT::i16:
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RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
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Chain = RetVal.getValue(1);
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break;
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case MVT::i32:
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RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
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Chain = RetVal.getValue(1);
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break;
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case MVT::i64: {
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SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
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SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
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Lo.getValue(2));
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RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
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Chain = Hi.getValue(1);
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break;
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}
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case MVT::f32:
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case MVT::f64: {
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std::vector<MVT::ValueType> Tys;
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Tys.push_back(MVT::f64);
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Tys.push_back(MVT::Other);
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std::vector<SDOperand> Ops;
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Ops.push_back(Chain);
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Ops.push_back(InFlag);
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RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
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Chain = RetVal.getValue(1);
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if (X86ScalarSSE) {
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unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
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MachineFunction &MF = DAG.getMachineFunction();
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int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
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SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
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Tys.clear();
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Tys.push_back(MVT::Other);
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Ops.clear();
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Ops.push_back(Chain);
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Ops.push_back(RetVal);
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Ops.push_back(StackSlot);
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Ops.push_back(DAG.getValueType(RetTyVT));
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Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
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RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
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DAG.getSrcValue(NULL));
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Chain = RetVal.getValue(1);
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} else if (RetTyVT == MVT::f32)
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RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
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break;
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}
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}
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}
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Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
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DAG.getConstant(NumBytes, getPointerTy()),
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DAG.getConstant(0, getPointerTy()));
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return std::make_pair(RetVal, Chain);
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} else {
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std::vector<SDOperand> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
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Ops.push_back(DAG.getConstant(0, getPointerTy()));
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SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
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RetVals, Ops);
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SDOperand ResultVal;
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switch (RetTyVT) {
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case MVT::isVoid: break;
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default:
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ResultVal = TheCall.getValue(1);
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
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break;
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case MVT::f32:
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// FIXME: we would really like to remember that this FP_ROUND operation is
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// okay to eliminate if we allow excess FP precision.
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ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
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break;
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case MVT::i64:
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ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
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TheCall.getValue(2));
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break;
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}
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Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
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return std::make_pair(ResultVal, Chain);
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}
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return std::make_pair(ResultVal, Chain);
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}
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SDOperand
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@ -1085,6 +1164,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
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case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
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case X86ISD::FLD: return "X86ISD::FLD";
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case X86ISD::FST: return "X86ISD::FST";
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case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
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case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
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case X86ISD::CALL: return "X86ISD::CALL";
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case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
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@ -46,6 +46,17 @@ namespace llvm {
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/// to load to.
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FLD,
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/// FST - This instruction implements a truncating store to FP stack
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/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
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/// chain operand, value to store, address, and a ValueType to store it
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/// as.
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FST,
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/// FP_SET_RESULT - This corresponds to FpGETRESULT pseudo instrcuction
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/// which copies from ST(0) to the destination. It takes a chain and writes
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/// a RFP result and a chain.
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FP_GET_RESULT,
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/// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instrcuction
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/// which copies the source operand to ST(0). It takes a chain and writes
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/// a chain and a flag.
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@ -36,7 +36,11 @@ def SDTX86RetFlag : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
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def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
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SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
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def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
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SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
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def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>;
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def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
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def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, []>;
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@ -49,10 +53,24 @@ def X86SetCC : SDNode<"X86ISD::SETCC", SDTX86SetCC, []>;
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def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86RetFlag, [SDNPHasChain]>;
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def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, [SDNPHasChain]>;
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def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, [SDNPHasChain]>;
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def X86fpget : SDNode<"X86ISD::FP_GET_RESULT",
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SDTX86FpGet, [SDNPHasChain]>;
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def X86fpset : SDNode<"X86ISD::FP_SET_RESULT",
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SDTX86FpSet, [SDNPHasChain]>;
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def SDT_X86CallSeqStart : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
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def SDT_X86CallSeqEnd : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
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SDTCisVT<1, i32> ]>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
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[SDNPHasChain]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
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[SDNPHasChain]>;
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def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
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def call : SDNode<"X86ISD::CALL", SDT_X86Call, [SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// X86 Operand Definitions.
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//
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@ -275,9 +293,11 @@ class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
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def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE", []>; // PHI node.
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def NOOP : I<0x90, RawFrm, (ops), "nop", []>; // nop
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def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN", []>;
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def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN",
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[(callseq_start imm:$amt)]>;
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def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),
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"#ADJCALLSTACKUP", []>;
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"#ADJCALLSTACKUP",
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[(callseq_end imm:$amt1, imm:$amt2)]>;
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def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>;
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def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>;
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let isTerminator = 1 in
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@ -301,9 +321,6 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
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}
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}
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def : Pat<(X86retflag 0), (RET)>;
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def : Pat<(X86retflag imm:$amt), (RETI imm:$amt)>;
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// All branches are RawFrm, Void, Branch, and Terminators
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let isBranch = 1, isTerminator = 1, noResults = 1 in
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class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> :
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@ -342,15 +359,25 @@ def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst", []>, TB;
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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let isCall = 1, noResults = 1 in
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// FIXME: How about hasInFlag = 1? A fastcall would require an incoming flag
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// to stick the CopyToRegs to the call.
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let isCall = 1, noResults = 1, hasOutFlag = 1 in
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// All calls clobber the non-callee saved registers...
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let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
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def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst", []>;
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def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst", []>;
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def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst", []>;
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def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst",
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[]>;
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def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst",
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[]>;
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def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst",
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[]>;
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}
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def : Pat<(call tglobaladdr:$dst),
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(CALLpcrel32 tglobaladdr:$dst)>;
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def : Pat<(call externalsym:$dst),
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(CALLpcrel32 externalsym:$dst)>;
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// Tail call stuff.
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
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def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst # TAIL CALL", []>;
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@ -2309,11 +2336,17 @@ class FpI<dag ops, FPFormat fp, list<dag> pattern>
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}
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// Random Pseudo Instructions.
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def FpGETRESULT : FpI<(ops RFP:$dst), SpecialFP, []>; // FPR = ST(0)
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let hasInFlag = 1 in
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def FpGETRESULT : FpI<(ops RFP:$dst), SpecialFP, []>; // FPR = ST(0)
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// Do not inline into instruction def. since it isn't predicated on FPStack.
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def : Pat<(X86fpget), (FpGETRESULT)>;
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let noResults = 1, hasOutFlag = 1 in
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def FpSETRESULT : FpI<(ops RFP:$src), SpecialFP,
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[]>, Imp<[], [ST0]>; // ST(0) = FPR
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// Do not inline into instruction def. since it isn't predicated on FPStack.
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def : Pat<(X86fpset RFP:$src), (FpSETRESULT RFP:$src)>;
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def FpMOV : FpI<(ops RFP:$dst, RFP:$src), SpecialFP, []>; // f1 = fmov f2
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@ -2359,7 +2392,7 @@ def FpSUB64m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fsub RFP:$src1, (loadf64 addr:$src2)))]>;
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// ST(0) = ST(0) - [mem64]
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def FpSUBR32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
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[(set RFP:$dst, (fadd (extloadf64f32 addr:$src2),
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[(set RFP:$dst, (fsub (extloadf64f32 addr:$src2),
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RFP:$src1))]>;
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// ST(0) = [mem32] - ST(0)
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def FpSUBR64m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
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@ -2503,6 +2536,10 @@ def FpST32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP,
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[(truncstore RFP:$src, addr:$op, f32)]>;
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def FpST64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP,
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[(store RFP:$src, addr:$op)]>;
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def : Pat<(X86fst RFP:$src, addr:$op, f32), (FpST32m addr:$op, RFP:$src)>;
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def : Pat<(X86fst RFP:$src, addr:$op, f64), (FpST64m addr:$op, RFP:$src)>;
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def FpSTP32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP, []>;
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def FpSTP64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP, []>;
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def FpIST16m : FpI<(ops i16mem:$op, RFP:$src), OneArgFP, []>;
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