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For ARM load/store instructions, encode [reg+reg] with no shifter immediate as

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a left shift by zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-11-09 17:38:15 +00:00
parent a9a0dde872
commit d92354c574
1 changed files with 3 additions and 0 deletions
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3
lib/Target/ARM/ARMMCCodeEmitter.cpp
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@ -277,6 +277,9 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
// ROR - 11
switch (ShOp) {
default: llvm_unreachable("Unknown shift opc!");
case ARM_AM::no_shift:
assert(ShImm == 0 && "Non-zero shift amount with no shift type!");
// fall through
case ARM_AM::lsl: SBits = 0x0; break;
case ARM_AM::lsr: SBits = 0x1; break;
case ARM_AM::asr: SBits = 0x2; break;