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For ARM load/store instructions, encode [reg+reg] with no shifter immediate as
a left shift by zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -277,6 +277,9 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
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// ROR - 11
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switch (ShOp) {
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default: llvm_unreachable("Unknown shift opc!");
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case ARM_AM::no_shift:
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assert(ShImm == 0 && "Non-zero shift amount with no shift type!");
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// fall through
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case ARM_AM::lsl: SBits = 0x0; break;
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case ARM_AM::lsr: SBits = 0x1; break;
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case ARM_AM::asr: SBits = 0x2; break;
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