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some hoovering

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25643 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duraid Madina 2006-01-26 09:08:31 +00:00
parent 4dcfaac2e3
commit d92f116a1c
3 changed files with 13 additions and 9 deletions
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7
lib/Target/IA64/IA64Bundling.cpp
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@ -2,8 +2,8 @@
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file was developed by the LLVM research group and is distributed under // This file was developed by Duraid Madina and is distributed under the
// the University of Illinois Open Source License. See LICENSE.TXT for details. // University of Illinois Open Source License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
@ -56,7 +56,8 @@ namespace {
std::set<unsigned> PendingRegWrites; // XXX: ugly global, but std::set<unsigned> PendingRegWrites; // XXX: ugly global, but
// pending writes can cross basic blocks. Note that // pending writes can cross basic blocks. Note that
// taken branches end instruction groups. // taken branches end instruction groups. So we
// only need to worry about 'fallthrough' code
}; };
} // end of anonymous namespace } // end of anonymous namespace

7
lib/Target/IA64/IA64InstrInfo.td
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@ -501,10 +501,13 @@ def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm), def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
"shr $dst = $src1, $imm">; "shr $dst = $src1, $imm">;
def EXTRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), def EXTRU : AForm<0x03, 0x0b,
(ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
"extr.u $dst = $src1, $imm1, $imm2">; "extr.u $dst = $src1, $imm1, $imm2">;
def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2">; def DEPZ : AForm<0x03, 0x0b,
(ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
"dep.z $dst = $src1, $imm1, $imm2">;
def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp), def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
"($qp) cmp.eq.or $dst, p0 = $src1, $src2">; "($qp) cmp.eq.or $dst, p0 = $src1, $src2">;

8
lib/Target/IA64/IA64RegisterInfo.cpp
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@ -168,8 +168,8 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
if ( Offset <= 8191 && Offset >= -8192) { // smallish offset if ( Offset <= 8191 && Offset >= -8192) { // smallish offset
//fix up the old: //fix up the old:
MI.SetMachineOperandReg(i, IA64::r22); MI.SetMachineOperandReg(i, IA64::r22);
MachineOperand &MO = MI.getOperand(i); MI.getOperand(i).setUse(); // mark r22 as being used
MO.setUse(); // mark r22 as being used (the bundler wants to know this) // (the bundler wants to know this)
//insert the new //insert the new
MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22) MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
.addReg(BaseRegister).addSImm(Offset); .addReg(BaseRegister).addSImm(Offset);
@ -177,8 +177,8 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
} else { // it's big } else { // it's big
//fix up the old: //fix up the old:
MI.SetMachineOperandReg(i, IA64::r22); MI.SetMachineOperandReg(i, IA64::r22);
MachineOperand &MO = MI.getOperand(i); MI.getOperand(i).setUse(); // mark r22 as being used
MO.setUse(); // mark r22 as being used (the bundler wants to know this) // (the bundler wants to know this)
MachineInstr* nMI; MachineInstr* nMI;
nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(Offset); nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(Offset);
MBB.insert(II, nMI); MBB.insert(II, nMI);