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Post regalloc LICM. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100592 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -170,7 +170,7 @@ namespace llvm {
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/// createMachineLICMPass - This pass performs LICM on machine instructions.
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/// createMachineLICMPass - This pass performs LICM on machine instructions.
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///
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///
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FunctionPass *createMachineLICMPass();
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FunctionPass *createMachineLICMPass(bool PreRegAlloc = true);
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/// createMachineSinkingPass - This pass performs sinking on machine
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/// createMachineSinkingPass - This pass performs sinking on machine
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/// instructions.
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/// instructions.
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@ -66,6 +66,9 @@ static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
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cl::desc("Verify generated machine code"),
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cl::desc("Verify generated machine code"),
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cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
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cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
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static cl::opt<bool> PostRAMachineLICM("postra-machine-licm", cl::Hidden,
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cl::desc("Enable post-regalloc Machine LICM"));
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static cl::opt<cl::boolOrDefault>
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static cl::opt<cl::boolOrDefault>
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AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
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AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
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cl::init(cl::BOU_UNSET));
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cl::init(cl::BOU_UNSET));
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@ -343,6 +346,10 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
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// kill markers.
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// kill markers.
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PM.add(createStackSlotColoringPass(false));
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PM.add(createStackSlotColoringPass(false));
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printAndVerify(PM, "After StackSlotColoring");
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printAndVerify(PM, "After StackSlotColoring");
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// Run post-ra machine LICM to hoist reloads / remats.
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if (PostRAMachineLICM)
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PM.add(createMachineLICMPass(false));
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}
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}
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// Run post-ra passes.
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// Run post-ra passes.
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@ -22,8 +22,8 @@
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#define DEBUG_TYPE "machine-licm"
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#define DEBUG_TYPE "machine-licm"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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@ -33,6 +33,7 @@
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/raw_ostream.h"
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@ -41,20 +42,23 @@ using namespace llvm;
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STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops");
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STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops");
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STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed");
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STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed");
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STATISTIC(NumPostRAHoisted,
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"Number of machine instructions hoisted out of loops post regalloc");
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namespace {
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namespace {
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class MachineLICM : public MachineFunctionPass {
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class MachineLICM : public MachineFunctionPass {
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MachineConstantPool *MCP;
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bool PreRegAlloc;
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const TargetMachine *TM;
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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const TargetRegisterInfo *TRI;
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BitVector AllocatableSet;
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const MachineFrameInfo *MFI;
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MachineRegisterInfo *RegInfo;
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// Various analyses that we use...
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// Various analyses that we use...
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AliasAnalysis *AA; // Alias analysis info.
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AliasAnalysis *AA; // Alias analysis info.
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MachineLoopInfo *LI; // Current MachineLoopInfo
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MachineLoopInfo *LI; // Current MachineLoopInfo
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MachineDominatorTree *DT; // Machine dominator tree for the cur loop
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MachineDominatorTree *DT; // Machine dominator tree for the cur loop
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MachineRegisterInfo *RegInfo; // Machine register information
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// State that is updated as we process loops
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// State that is updated as we process loops
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bool Changed; // True if a loop is changed.
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bool Changed; // True if a loop is changed.
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@ -62,11 +66,18 @@ namespace {
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MachineLoop *CurLoop; // The current loop we are working on.
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MachineLoop *CurLoop; // The current loop we are working on.
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MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
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MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
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BitVector AllocatableSet;
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// For each opcode, keep a list of potentail CSE instructions.
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// For each opcode, keep a list of potentail CSE instructions.
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DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
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DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
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public:
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public:
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static char ID; // Pass identification, replacement for typeid
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static char ID; // Pass identification, replacement for typeid
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MachineLICM() : MachineFunctionPass(&ID) {}
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MachineLICM() :
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MachineFunctionPass(&ID), PreRegAlloc(true) {}
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explicit MachineLICM(bool PreRA) :
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MachineFunctionPass(&ID), PreRegAlloc(PreRA) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual bool runOnMachineFunction(MachineFunction &MF);
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@ -106,6 +117,7 @@ namespace {
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/// pass without iteration.
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/// pass without iteration.
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///
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///
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void HoistRegion(MachineDomTreeNode *N);
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void HoistRegion(MachineDomTreeNode *N);
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void HoistRegionPostRA(MachineDomTreeNode *N);
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/// isLoadFromConstantMemory - Return true if the given instruction is a
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/// isLoadFromConstantMemory - Return true if the given instruction is a
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/// load from constant memory.
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/// load from constant memory.
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@ -133,6 +145,7 @@ namespace {
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/// that is safe to hoist, this instruction is called to do the dirty work.
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/// that is safe to hoist, this instruction is called to do the dirty work.
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///
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///
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void Hoist(MachineInstr *MI);
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void Hoist(MachineInstr *MI);
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void HoistPostRA(MachineInstr *MI);
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/// InitCSEMap - Initialize the CSE map with instructions that are in the
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/// InitCSEMap - Initialize the CSE map with instructions that are in the
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/// current loop preheader that may become duplicates of instructions that
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/// current loop preheader that may become duplicates of instructions that
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@ -145,7 +158,9 @@ char MachineLICM::ID = 0;
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static RegisterPass<MachineLICM>
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static RegisterPass<MachineLICM>
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X("machinelicm", "Machine Loop Invariant Code Motion");
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X("machinelicm", "Machine Loop Invariant Code Motion");
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FunctionPass *llvm::createMachineLICMPass() { return new MachineLICM(); }
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FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) {
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return new MachineLICM(PreRegAlloc);
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}
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/// LoopIsOuterMostWithPreheader - Test if the given loop is the outer-most
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/// LoopIsOuterMostWithPreheader - Test if the given loop is the outer-most
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/// loop that has a preheader.
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/// loop that has a preheader.
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@ -161,13 +176,16 @@ static bool LoopIsOuterMostWithPreheader(MachineLoop *CurLoop) {
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/// loop.
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/// loop.
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///
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///
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bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
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bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(dbgs() << "******** Machine LICM ********\n");
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if (PreRegAlloc)
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DEBUG(dbgs() << "******** Pre-regalloc Machine LICM ********\n");
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else
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DEBUG(dbgs() << "******** Post-regalloc Machine LICM ********\n");
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Changed = FirstInLoop = false;
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Changed = FirstInLoop = false;
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MCP = MF.getConstantPool();
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TM = &MF.getTarget();
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TM = &MF.getTarget();
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TII = TM->getInstrInfo();
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TII = TM->getInstrInfo();
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TRI = TM->getRegisterInfo();
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TRI = TM->getRegisterInfo();
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MFI = MF.getFrameInfo();
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RegInfo = &MF.getRegInfo();
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RegInfo = &MF.getRegInfo();
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AllocatableSet = TRI->getAllocatableSet(MF);
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AllocatableSet = TRI->getAllocatableSet(MF);
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@ -196,13 +214,147 @@ bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
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// CSEMap is initialized for loop header when the first instruction is
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// CSEMap is initialized for loop header when the first instruction is
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// being hoisted.
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// being hoisted.
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FirstInLoop = true;
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FirstInLoop = true;
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HoistRegion(DT->getNode(CurLoop->getHeader()));
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MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
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CSEMap.clear();
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if (!PreRegAlloc)
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HoistRegionPostRA(N);
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else {
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HoistRegion(N);
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CSEMap.clear();
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}
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}
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}
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return Changed;
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return Changed;
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}
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}
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void MachineLICM::HoistRegionPostRA(MachineDomTreeNode *N) {
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assert(N != 0 && "Null dominator tree node?");
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unsigned NumRegs = TRI->getNumRegs();
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unsigned *PhysRegDefs = new unsigned[NumRegs];
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std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
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SmallVector<std::pair<MachineInstr*, int>, 32> Candidates;
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SmallSet<int, 32> StoredFIs;
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// Walk the entire region, count number of defs for each register, and
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// return potential LICM candidates.
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SmallVector<MachineDomTreeNode*, 8> WorkList;
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WorkList.push_back(N);
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do {
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N = WorkList.pop_back_val();
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MachineBasicBlock *BB = N->getBlock();
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if (!CurLoop->contains(BB))
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continue;
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// Conservatively treat live-in's as an external def.
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for (MachineBasicBlock::const_livein_iterator I = BB->livein_begin(),
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E = BB->livein_end(); I != E; ++I) {
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unsigned Reg = *I;
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++PhysRegDefs[Reg];
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for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR)
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++PhysRegDefs[*SR];
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}
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for (MachineBasicBlock::iterator
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MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
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bool RuledOut = false;
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bool SeenDef = false;
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MachineInstr *MI = &*MII;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
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"Not expecting virtual register!");
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if (MO.isDef()) {
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SeenDef = true;
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if (++PhysRegDefs[Reg] > 1)
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// MI defined register is seen defined by another instruction in
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// the loop, it cannot be a LICM candidate.
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RuledOut = true;
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for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR)
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if (++PhysRegDefs[*SR] > 1)
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RuledOut = true;
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}
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}
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// FIXME: Only consider reloads for now.
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bool SkipCheck = false;
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int FI;
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if (SeenDef && !RuledOut) {
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if (TII->isLoadFromStackSlot(MI, FI) &&
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MFI->isSpillSlotObjectIndex(FI)) {
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Candidates.push_back(std::make_pair(MI, FI));
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SkipCheck = true;
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}
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}
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// If MI is a store to a stack slot, remember the slot. An instruction
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// loads from this slot cannot be a LICM candidate.
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if (SkipCheck && TII->isStoreToStackSlot(MI, FI))
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StoredFIs.insert(FI);
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}
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const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
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for (unsigned I = 0, E = Children.size(); I != E; ++I)
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WorkList.push_back(Children[I]);
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} while (!WorkList.empty());
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// Now evaluate whether the potential candidates qualify.
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// 1. Check if the candidate defined register is defined by another
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// instruction in the loop.
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// 2. If the candidate is a load from stack slot (always true for now),
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// check if the slot is stored anywhere in the loop.
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for (unsigned i = 0, e = Candidates.size(); i != e; ++i) {
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bool Safe = true;
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int FI = Candidates[i].second;
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if (StoredFIs.count(FI))
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continue;
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MachineInstr *MI = Candidates[i].first;
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for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
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const MachineOperand &MO = MI->getOperand(j);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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if (MO.isDef() && PhysRegDefs[Reg] > 1) {
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Safe = false;
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break;
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}
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}
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if (Safe)
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HoistPostRA(MI);
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}
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}
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void MachineLICM::HoistPostRA(MachineInstr *MI) {
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// Now move the instructions to the predecessor, inserting it before any
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// terminator instructions.
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DEBUG({
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dbgs() << "Hoisting " << *MI;
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if (CurPreheader->getBasicBlock())
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dbgs() << " to MachineBasicBlock "
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<< CurPreheader->getName();
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if (MI->getParent()->getBasicBlock())
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dbgs() << " from MachineBasicBlock "
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<< MI->getParent()->getName();
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dbgs() << "\n";
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});
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// Splice the instruction to the preheader.
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CurPreheader->splice(CurPreheader->getFirstTerminator(),MI->getParent(),MI);
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++NumPostRAHoisted;
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Changed = true;
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}
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/// HoistRegion - Walk the specified region of the CFG (defined by all blocks
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/// HoistRegion - Walk the specified region of the CFG (defined by all blocks
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/// dominated by the specified block, and that are in the current loop) in depth
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/// dominated by the specified block, and that are in the current loop) in depth
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/// first order w.r.t the DominatorTree. This allows us to visit definitions
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/// first order w.r.t the DominatorTree. This allows us to visit definitions
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@ -223,7 +375,6 @@ void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
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}
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}
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const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
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const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
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for (unsigned I = 0, E = Children.size(); I != E; ++I)
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for (unsigned I = 0, E = Children.size(); I != E; ++I)
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HoistRegion(Children[I]);
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HoistRegion(Children[I]);
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}
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}
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