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[mips][mips64r6] madd/maddu/msub/msubu are not available on MIPS32r6/MIPS64r6
Summary: This patch disables madd/maddu/msub/msubu in both the assembler and code generator. Depends on D3896 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3955 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210762 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
bf4e625cf1
commit
d94bc707c4
@ -36,7 +36,6 @@ include "Mips32r6InstrFormats.td"
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// Removed: luxc1
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// Removed: lwxc1
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// Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
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// Removed: madd, maddu, msub, msubu
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// Removed: movf, movt
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// Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
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// Removed: movn, movz
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@ -1247,10 +1247,14 @@ def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
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def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
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// MADD*/MSUB*
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def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>, ISA_MIPS32;
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def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>, ISA_MIPS32;
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def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>, ISA_MIPS32;
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def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>, ISA_MIPS32;
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def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
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ISA_MIPS32_NOT_32R6_64R6;
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def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
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ISA_MIPS32_NOT_32R6_64R6;
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def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
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ISA_MIPS32_NOT_32R6_64R6;
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def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
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ISA_MIPS32_NOT_32R6_64R6;
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let AdditionalPredicates = [NotDSP] in {
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def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
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@ -1260,10 +1264,14 @@ def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
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def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
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def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
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def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
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def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
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def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
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def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
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def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
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def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
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ISA_MIPS32_NOT_32R6_64R6;
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def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
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ISA_MIPS32_NOT_32R6_64R6;
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def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
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ISA_MIPS32_NOT_32R6_64R6;
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def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
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ISA_MIPS32_NOT_32R6_64R6;
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}
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def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
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@ -155,6 +155,8 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
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if (Subtarget->hasMips32r6()) {
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// MIPS32r6 replaces the accumulator-based multiplies with a three register
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// instruction
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setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::MUL, MVT::i32, Legal);
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setOperationAction(ISD::MULHS, MVT::i32, Legal);
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setOperationAction(ISD::MULHU, MVT::i32, Legal);
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@ -483,8 +485,8 @@ static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
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if (DCI.isBeforeLegalize())
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return SDValue();
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if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
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selectMADD(N, &DAG))
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if (Subtarget->hasMips32() && !Subtarget->hasMips32r6() &&
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N->getValueType(0) == MVT::i32 && selectMADD(N, &DAG))
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return SDValue(N, 0);
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return SDValue();
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@ -1,4 +1,4 @@
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; RUN: llc -march=mipsel -mattr=+dsp < %s | FileCheck %s
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; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp < %s | FileCheck %s
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define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind {
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entry:
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@ -1,9 +1,49 @@
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; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=32
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; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=DSP
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; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32
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; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32
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; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R6
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; RUN: llc -march=mips -mcpu=mips32 -mattr=dsp < %s | FileCheck %s -check-prefix=DSP
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; RUN: llc -march=mips -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64
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; RUN: llc -march=mips -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64
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; RUN: llc -march=mips -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64R6
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; FIXME: The MIPS16 test should check its output
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; RUN: llc -march=mips -mcpu=mips16 < %s
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; 32: madd ${{[0-9]+}}
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; DSP: madd $ac
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; ALL-LABEL: madd1:
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; 32-DAG: sra $[[T0:[0-9]+]], $6, 31
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; 32-DAG: mtlo $6
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; 32-DAG: [[m:m]]add ${{[45]}}, ${{[45]}}
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; 32-DAG: [[m]]fhi $2
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; 32-DAG: [[m]]flo $3
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; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31
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; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
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; DSP-DAG: madd $[[AC]], ${{[45]}}, ${{[45]}}
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; DSP-DAG: mfhi $2, $[[AC]]
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; DSP-DAG: mflo $3, $[[AC]]
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; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $6
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; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $6
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; 32R6-DAG: sra $[[T3:[0-9]+]], $6, 31
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; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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; 32R6-DAG: muh $[[T5:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: addu $2, $[[T5]], $[[T4]]
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; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
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; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
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; 64-DAG: sll $[[T3:[0-9]+]], $6, 0
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; 64-DAG: daddu $2, $[[T2]], $[[T3]]
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; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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; 64R6-DAG: sll $[[T3:[0-9]+]], $6, 0
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; 64R6-DAG: daddu $2, $[[T2]], $[[T3]]
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define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone {
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entry:
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%conv = sext i32 %a to i64
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@ -14,8 +54,47 @@ entry:
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ret i64 %add
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}
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; 32: maddu ${{[0-9]+}}
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; DSP: maddu $ac
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; ALL-LABEL: madd2:
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; FIXME: We don't really need this instruction
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; 32-DAG: addiu $[[T0:[0-9]+]], $zero, 0
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; 32-DAG: mtlo $6
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; 32-DAG: [[m:m]]addu ${{[45]}}, ${{[45]}}
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; 32-DAG: [[m]]fhi $2
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; 32-DAG: [[m]]flo $3
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; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0
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; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
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; DSP-DAG: maddu $[[AC]], ${{[45]}}, ${{[45]}}
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; DSP-DAG: mfhi $2, $[[AC]]
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; DSP-DAG: mflo $3, $[[AC]]
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; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $6
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; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $6
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; FIXME: There's a redundant move here. We should remove it
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; 32R6-DAG: muhu $[[T3:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: addu $2, $[[T3]], $[[T2]]
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; 64-DAG: dsll $[[T0:[0-9]+]], $4, 32
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; 64-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
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; 64-DAG: dsll $[[T2:[0-9]+]], $5, 32
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; 64-DAG: dsrl $[[T3:[0-9]+]], $[[T2]], 32
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; 64-DAG: d[[m:m]]ult $[[T3]], $[[T1]]
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; 64-DAG: [[m]]flo $[[T4:[0-9]+]]
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; 64-DAG: dsll $[[T5:[0-9]+]], $6, 32
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; 64-DAG: dsrl $[[T6:[0-9]+]], $[[T5]], 32
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; 64-DAG: daddu $2, $[[T4]], $[[T6]]
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; 64R6-DAG: dsll $[[T0:[0-9]+]], $4, 32
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; 64R6-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
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; 64R6-DAG: dsll $[[T2:[0-9]+]], $5, 32
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; 64R6-DAG: dsrl $[[T3:[0-9]+]], $[[T2]], 32
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; 64R6-DAG: dmul $[[T4:[0-9]+]], $[[T3]], $[[T1]]
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; 64R6-DAG: dsll $[[T5:[0-9]+]], $6, 32
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; 64R6-DAG: dsrl $[[T6:[0-9]+]], $[[T5]], 32
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; 64R6-DAG: daddu $2, $[[T4]], $[[T6]]
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define i64 @madd2(i32 %a, i32 %b, i32 %c) nounwind readnone {
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entry:
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%conv = zext i32 %a to i64
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@ -26,8 +105,38 @@ entry:
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ret i64 %add
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}
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; 32: madd ${{[0-9]+}}
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; DSP: madd $ac
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; ALL-LABEL: madd3:
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; 32-DAG: mthi $6
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; 32-DAG: mtlo $7
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; 32-DAG: [[m:m]]add ${{[45]}}, ${{[45]}}
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; 32-DAG: [[m]]fhi $2
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; 32-DAG: [[m]]flo $3
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; DSP-DAG: mthi $[[AC:ac[0-3]+]], $6
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; DSP-DAG: mtlo $[[AC]], $7
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; DSP-DAG: madd $[[AC]], ${{[45]}}, ${{[45]}}
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; DSP-DAG: mfhi $2, $[[AC]]
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; DSP-DAG: mflo $3, $[[AC]]
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; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $7
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; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $7
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; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T2]], $6
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; 32R6-DAG: muh $[[T5:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: addu $2, $[[T5]], $[[T4]]
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; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
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; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
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; 64-DAG: daddu $2, $[[T2]], $6
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; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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; 64R6-DAG: daddu $2, $[[T2]], $6
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define i64 @madd3(i32 %a, i32 %b, i64 %c) nounwind readnone {
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entry:
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%conv = sext i32 %a to i64
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@ -37,8 +146,41 @@ entry:
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ret i64 %add
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}
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; 32: msub ${{[0-9]+}}
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; DSP: msub $ac
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; ALL-LABEL: msub1:
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; 32-DAG: sra $[[T0:[0-9]+]], $6, 31
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; 32-DAG: mtlo $6
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; 32-DAG: [[m:m]]sub ${{[45]}}, ${{[45]}}
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; 32-DAG: [[m]]fhi $2
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; 32-DAG: [[m]]flo $3
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; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31
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; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
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; DSP-DAG: msub $[[AC]], ${{[45]}}, ${{[45]}}
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; DSP-DAG: mfhi $2, $[[AC]]
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; DSP-DAG: mflo $3, $[[AC]]
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; 32R6-DAG: muh $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: sltu $[[T3:[0-9]+]], $6, $[[T1]]
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; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T3]], $[[T0]]
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; 32R6-DAG: sra $[[T5:[0-9]+]], $6, 31
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; 32R6-DAG: subu $2, $[[T5]], $[[T4]]
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; 32R6-DAG: subu $3, $6, $[[T1]]
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; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
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; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
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; 64-DAG: sll $[[T3:[0-9]+]], $6, 0
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; 64-DAG: dsubu $2, $[[T3]], $[[T2]]
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; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
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; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
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; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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; 64R6-DAG: sll $[[T3:[0-9]+]], $6, 0
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; 64R6-DAG: dsubu $2, $[[T3]], $[[T2]]
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define i64 @msub1(i32 %a, i32 %b, i32 %c) nounwind readnone {
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entry:
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%conv = sext i32 %c to i64
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@ -49,8 +191,48 @@ entry:
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ret i64 %sub
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}
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; 32: msubu ${{[0-9]+}}
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; DSP: msubu $ac
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; ALL-LABEL: msub2:
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; FIXME: We don't really need this instruction
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; 32-DAG: addiu $[[T0:[0-9]+]], $zero, 0
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; 32-DAG: mtlo $6
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; 32-DAG: [[m:m]]subu ${{[45]}}, ${{[45]}}
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; 32-DAG: [[m]]fhi $2
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; 32-DAG: [[m]]flo $3
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; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0
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; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
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; DSP-DAG: msubu $[[AC]], ${{[45]}}, ${{[45]}}
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; DSP-DAG: mfhi $2, $[[AC]]
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; DSP-DAG: mflo $3, $[[AC]]
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; 32R6-DAG: muhu $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
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; 32R6-DAG: sltu $[[T2:[0-9]+]], $6, $[[T1]]
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; 32R6-DAG: addu $[[T3:[0-9]+]], $[[T2]], $[[T0]]
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; 32R6-DAG: negu $2, $[[T3]]
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; 32R6-DAG: subu $3, $6, $[[T1]]
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; 64-DAG: dsll $[[T0:[0-9]+]], $4, 32
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; 64-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
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; 64-DAG: dsll $[[T2:[0-9]+]], $5, 32
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; 64-DAG: dsrl $[[T3:[0-9]+]], $[[T2]], 32
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; 64-DAG: d[[m:m]]ult $[[T3]], $[[T1]]
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; 64-DAG: [[m]]flo $[[T4:[0-9]+]]
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; 64-DAG: dsll $[[T5:[0-9]+]], $6, 32
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; 64-DAG: dsrl $[[T6:[0-9]+]], $[[T5]], 32
|
||||
; 64-DAG: dsubu $2, $[[T6]], $[[T4]]
|
||||
|
||||
; 64R6-DAG: dsll $[[T0:[0-9]+]], $4, 32
|
||||
; 64R6-DAG: dsrl $[[T1:[0-9]+]], $[[T0]], 32
|
||||
; 64R6-DAG: dsll $[[T2:[0-9]+]], $5, 32
|
||||
; 64R6-DAG: dsrl $[[T3:[0-9]+]], $[[T2]], 32
|
||||
; 64R6-DAG: dmul $[[T4:[0-9]+]], $[[T3]], $[[T1]]
|
||||
; 64R6-DAG: dsll $[[T5:[0-9]+]], $6, 32
|
||||
; 64R6-DAG: dsrl $[[T6:[0-9]+]], $[[T5]], 32
|
||||
; 64R6-DAG: dsubu $2, $[[T6]], $[[T4]]
|
||||
|
||||
define i64 @msub2(i32 %a, i32 %b, i32 %c) nounwind readnone {
|
||||
entry:
|
||||
%conv = zext i32 %c to i64
|
||||
@ -61,8 +243,39 @@ entry:
|
||||
ret i64 %sub
|
||||
}
|
||||
|
||||
; 32: msub ${{[0-9]+}}
|
||||
; DSP: msub $ac
|
||||
; ALL-LABEL: msub3:
|
||||
|
||||
; FIXME: We don't really need this instruction
|
||||
; 32-DAG: mthi $6
|
||||
; 32-DAG: mtlo $7
|
||||
; 32-DAG: [[m:m]]sub ${{[45]}}, ${{[45]}}
|
||||
; 32-DAG: [[m]]fhi $2
|
||||
; 32-DAG: [[m]]flo $3
|
||||
|
||||
; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0
|
||||
; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
|
||||
; DSP-DAG: msub $[[AC]], ${{[45]}}, ${{[45]}}
|
||||
; DSP-DAG: mfhi $2, $[[AC]]
|
||||
; DSP-DAG: mflo $3, $[[AC]]
|
||||
|
||||
; 32R6-DAG: muh $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
|
||||
; 32R6-DAG: mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
|
||||
; 32R6-DAG: sltu $[[T2:[0-9]+]], $7, $[[T1]]
|
||||
; 32R6-DAG: addu $[[T3:[0-9]+]], $[[T2]], $[[T0]]
|
||||
; 32R6-DAG: subu $2, $6, $[[T3]]
|
||||
; 32R6-DAG: subu $3, $7, $[[T1]]
|
||||
|
||||
; 64-DAG: sll $[[T0:[0-9]+]], $4, 0
|
||||
; 64-DAG: sll $[[T1:[0-9]+]], $5, 0
|
||||
; 64-DAG: d[[m:m]]ult $[[T1]], $[[T0]]
|
||||
; 64-DAG: [[m]]flo $[[T2:[0-9]+]]
|
||||
; 64-DAG: dsubu $2, $6, $[[T2]]
|
||||
|
||||
; 64R6-DAG: sll $[[T0:[0-9]+]], $4, 0
|
||||
; 64R6-DAG: sll $[[T1:[0-9]+]], $5, 0
|
||||
; 64R6-DAG: dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
|
||||
; 64R6-DAG: dsubu $2, $6, $[[T2]]
|
||||
|
||||
define i64 @msub3(i32 %a, i32 %b, i64 %c) nounwind readnone {
|
||||
entry:
|
||||
%conv = sext i32 %a to i64
|
||||
|
||||
13
test/MC/Mips/mips32r6/invalid-mips32.s
Normal file
13
test/MC/Mips/mips32r6/invalid-mips32.s
Normal file
@ -0,0 +1,13 @@
|
||||
# Instructions that are invalid
|
||||
#
|
||||
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
|
||||
# RUN: 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
.set noat
|
||||
madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
Loading…
x
Reference in New Issue
Block a user