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Add a 256-bit register class and YMM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74469 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -785,6 +785,11 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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}
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}
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if (!UseSoftFloat && Subtarget->hasAVX()) {
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if (!UseSoftFloat && Subtarget->hasAVX()) {
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addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
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addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
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addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
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addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
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setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
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setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
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setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
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setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
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setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
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setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
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@ -157,6 +157,24 @@ let Namespace = "X86" in {
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def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
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def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
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def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
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def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
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// YMM Registers, used by AVX instructions
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def YMM0: Register<"ymm0">, DwarfRegNum<[17, 21, 21]>;
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def YMM1: Register<"ymm1">, DwarfRegNum<[18, 22, 22]>;
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def YMM2: Register<"ymm2">, DwarfRegNum<[19, 23, 23]>;
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def YMM3: Register<"ymm3">, DwarfRegNum<[20, 24, 24]>;
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def YMM4: Register<"ymm4">, DwarfRegNum<[21, 25, 25]>;
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def YMM5: Register<"ymm5">, DwarfRegNum<[22, 26, 26]>;
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def YMM6: Register<"ymm6">, DwarfRegNum<[23, 27, 27]>;
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def YMM7: Register<"ymm7">, DwarfRegNum<[24, 28, 28]>;
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def YMM8: Register<"ymm8">, DwarfRegNum<[25, -2, -2]>;
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def YMM9: Register<"ymm9">, DwarfRegNum<[26, -2, -2]>;
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def YMM10: Register<"ymm10">, DwarfRegNum<[27, -2, -2]>;
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def YMM11: Register<"ymm11">, DwarfRegNum<[28, -2, -2]>;
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def YMM12: Register<"ymm12">, DwarfRegNum<[29, -2, -2]>;
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def YMM13: Register<"ymm13">, DwarfRegNum<[30, -2, -2]>;
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def YMM14: Register<"ymm14">, DwarfRegNum<[31, -2, -2]>;
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def YMM15: Register<"ymm15">, DwarfRegNum<[32, -2, -2]>;
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// Floating point stack registers
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// Floating point stack registers
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def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;
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def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;
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def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>;
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def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>;
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@ -229,6 +247,11 @@ def : SubRegSet<4, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
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[EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
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[EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
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R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>;
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R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>;
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def : SubRegSet<1, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
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YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15],
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Register Class Definitions... now that we have all of the pieces, define the
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// Register Class Definitions... now that we have all of the pieces, define the
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// top-level register classes. The order specified in the register list is
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// top-level register classes. The order specified in the register list is
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@ -755,6 +778,10 @@ def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
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}
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}
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}];
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}];
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}
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}
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def VR256 : RegisterClass<"X86", [ v8i32, v4i64, v8f32, v4f64],256,
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[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
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YMM8, YMM9, YMM10, YMM11,
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YMM12, YMM13, YMM14, YMM15]>;
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// Status flags registers.
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// Status flags registers.
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def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
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def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
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