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https://github.com/c64scene-ar/llvm-6502.git
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Last few SSE3 intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27711 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
de6df88529
commit
d953947d26
@ -466,6 +466,16 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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//===----------------------------------------------------------------------===//
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// SSE3
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// Addition / subtraction ops.
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse3_addsub_ps : GCCBuiltin<"__builtin_ia32_addsubps">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_v4f32_ty], [IntrNoMem]>;
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def int_x86_sse3_addsub_pd : GCCBuiltin<"__builtin_ia32_addsubpd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty], [IntrNoMem]>;
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}
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// Horizontal ops.
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse3_hadd_ps : GCCBuiltin<"__builtin_ia32_haddps">,
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@ -481,3 +491,19 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v2f64_ty], [IntrNoMem]>;
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}
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// Specialized unaligned load.
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse3_ldu_dq : GCCBuiltin<"__builtin_ia32_lddqu">,
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Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [IntrReadMem]>;
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}
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// Thread synchronization ops.
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse3_monitor : GCCBuiltin<"__builtin_ia32_monitor">,
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Intrinsic<[llvm_void_ty, llvm_ptr_ty,
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llvm_uint_ty, llvm_uint_ty], [IntrWriteMem]>;
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def int_x86_sse3_mwait : GCCBuiltin<"__builtin_ia32_mwait">,
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Intrinsic<[llvm_void_ty, llvm_uint_ty,
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llvm_uint_ty], [IntrWriteMem]>;
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}
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@ -1715,6 +1715,58 @@ bool X86::isMOVSMask(SDNode *N) {
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return true;
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}
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/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
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bool X86::isMOVSHDUPMask(SDNode *N) {
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assert(N->getOpcode() == ISD::BUILD_VECTOR);
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if (N->getNumOperands() != 4)
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return false;
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// Expect 1, 1, 3, 3
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for (unsigned i = 0; i < 2; ++i) {
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SDOperand Arg = N->getOperand(i);
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if (Arg.getOpcode() == ISD::UNDEF) continue;
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assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
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unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
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if (Val != 1) return false;
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}
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for (unsigned i = 2; i < 4; ++i) {
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SDOperand Arg = N->getOperand(i);
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if (Arg.getOpcode() == ISD::UNDEF) continue;
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assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
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unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
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if (Val != 3) return false;
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}
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return true;
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}
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/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
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bool X86::isMOVSLDUPMask(SDNode *N) {
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assert(N->getOpcode() == ISD::BUILD_VECTOR);
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if (N->getNumOperands() != 4)
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return false;
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// Expect 0, 0, 2, 2
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for (unsigned i = 0; i < 2; ++i) {
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SDOperand Arg = N->getOperand(i);
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if (Arg.getOpcode() == ISD::UNDEF) continue;
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assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
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unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
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if (Val != 0) return false;
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}
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for (unsigned i = 2; i < 4; ++i) {
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SDOperand Arg = N->getOperand(i);
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if (Arg.getOpcode() == ISD::UNDEF) continue;
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assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
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unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
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if (Val != 2) return false;
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}
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return true;
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}
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/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
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/// a splat of a single element.
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bool X86::isSplatMask(SDNode *N) {
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@ -2710,8 +2762,9 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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if (NumElems == 2)
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return Op;
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if (X86::isMOVSMask(PermMask.Val))
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// Leave the VECTOR_SHUFFLE alone. It matches MOVS{S|D}.
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if (X86::isMOVSMask(PermMask.Val) ||
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X86::isMOVSHDUPMask(PermMask.Val) ||
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X86::isMOVSLDUPMask(PermMask.Val))
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return Op;
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if (X86::isUNPCKLMask(PermMask.Val) ||
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@ -3143,6 +3196,8 @@ X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
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return (Mask.Val->getNumOperands() == 2 ||
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X86::isSplatMask(Mask.Val) ||
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X86::isMOVSMask(Mask.Val) ||
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X86::isMOVSHDUPMask(Mask.Val) ||
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X86::isMOVSLDUPMask(Mask.Val) ||
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X86::isPSHUFDMask(Mask.Val) ||
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isPSHUFHW_PSHUFLWMask(Mask.Val) ||
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X86::isSHUFPMask(Mask.Val) ||
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@ -237,6 +237,14 @@ namespace llvm {
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/// specifies a shuffle of elements that is suitable for input to MOVS{S|D}.
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bool isMOVSMask(SDNode *N);
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/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
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bool isMOVSHDUPMask(SDNode *N);
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/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
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bool isMOVSLDUPMask(SDNode *N);
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/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a splat of a single element.
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bool isSplatMask(SDNode *N);
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@ -88,6 +88,10 @@ def SSE_splat_mask : PatLeaf<(build_vector), [{
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return X86::isSplatMask(N);
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}], SHUFFLE_get_shuf_imm>;
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def SSE_splat_v2_mask : PatLeaf<(build_vector), [{
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return X86::isSplatMask(N);
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}]>;
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def MOVLHPS_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isMOVLHPSMask(N);
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}]>;
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@ -108,6 +112,14 @@ def MOVS_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isMOVSMask(N);
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}]>;
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def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isMOVSHDUPMask(N);
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}]>;
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def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isMOVSLDUPMask(N);
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}]>;
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def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKLMask(N);
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}]>;
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@ -155,8 +167,9 @@ def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
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// PDI - SSE2 instructions with TB and OpSize prefixes.
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// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
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// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
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// S3I - SSE3 instructions with TB and OpSize prefixes.
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// S3SI - SSE3 instructions with XS prefix.
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// S3SI - SSE3 instructions with XD prefix.
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// S3DI - SSE3 instructions with TB and OpSize prefixes.
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class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
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class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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@ -174,8 +187,10 @@ class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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let Pattern = pattern;
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}
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class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
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: I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE3]>;
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class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
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class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
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//===----------------------------------------------------------------------===//
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@ -232,18 +247,18 @@ class PD_Intrm<bits<8> o, string asm, Intrinsic IntId>
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: PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
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[(set VR128:$dst, (IntId VR128:$src1, (loadv2f64 addr:$src2)))]>;
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class S3S_Intrr<bits<8> o, string asm, Intrinsic IntId>
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: S3SI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
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[(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
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class S3S_Intrm<bits<8> o, string asm, Intrinsic IntId>
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: S3SI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
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[(set VR128:$dst, (v4f32 (IntId VR128:$src1,
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(loadv4f32 addr:$src2))))]>;
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class S3D_Intrr<bits<8> o, string asm, Intrinsic IntId>
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: S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
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[(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
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[(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
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class S3D_Intrm<bits<8> o, string asm, Intrinsic IntId>
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: S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
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[(set VR128:$dst, (v4f32 (IntId VR128:$src1,
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(loadv4f32 addr:$src2))))]>;
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class S3_Intrr<bits<8> o, string asm, Intrinsic IntId>
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: S3I<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
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[(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
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class S3_Intrm<bits<8> o, string asm, Intrinsic IntId>
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: S3I<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
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[(set VR128:$dst, (v2f64 (IntId VR128:$src1,
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(loadv2f64 addr:$src2))))]>;
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@ -528,6 +543,13 @@ def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
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"cvtss2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse_cvtss2si
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(loadv4f32 addr:$src)))]>;
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def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
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"cvtsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
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def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src),
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"cvtsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse2_cvtsd2si
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(loadv2f64 addr:$src)))]>;
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// Aliases for intrinsics
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def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
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@ -714,7 +736,7 @@ def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2)
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}
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//===----------------------------------------------------------------------===//
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// SSE packed FP Instructions
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// SSE packed Instructions
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//===----------------------------------------------------------------------===//
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// Some 'special' instructions
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@ -766,6 +788,9 @@ def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
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"movdqu {$src, $dst|$dst, $src}",
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[(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
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XS, Requires<[HasSSE2]>;
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def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
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"lddqu {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
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let isTwoAddress = 1 in {
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def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
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@ -833,6 +858,39 @@ def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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MOVHLPS_shuffle_mask)))]>;
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}
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def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"movshdup {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v4f32 (vector_shuffle
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VR128:$src, (undef),
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MOVSHDUP_shuffle_mask)))]>;
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def MOVSHDUPrm : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
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"movshdup {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v4f32 (vector_shuffle
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(loadv4f32 addr:$src), (undef),
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MOVSHDUP_shuffle_mask)))]>;
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def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"movsldup {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v4f32 (vector_shuffle
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VR128:$src, (undef),
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MOVSLDUP_shuffle_mask)))]>;
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def MOVSLDUPrm : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
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"movsldup {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v4f32 (vector_shuffle
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(loadv4f32 addr:$src), (undef),
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MOVSLDUP_shuffle_mask)))]>;
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def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"movddup {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v2f64 (vector_shuffle
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VR128:$src, (undef),
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SSE_splat_v2_mask)))]>;
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def MOVDDUPrm : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
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"movddup {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v2f64 (vector_shuffle
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(loadv2f64 addr:$src), (undef),
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SSE_splat_v2_mask)))]>;
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// SSE2 instructions without OpSize prefix
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def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"cvtdq2ps {$src, $dst|$dst, $src}",
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@ -910,15 +968,6 @@ def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
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[(set VR128:$dst, (int_x86_sse2_cvtpd2ps
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(loadv2f64 addr:$src)))]>;
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def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
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"cvtsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
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def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src),
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"cvtsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse2_cvtsd2si
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(loadv2f64 addr:$src)))]>;
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// Match intrinsics which expect XMM operand(s).
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// Aliases for intrinsics
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let isTwoAddress = 1 in {
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@ -1019,6 +1068,27 @@ def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"subpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (v2f64 (fsub VR128:$src1,
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(load addr:$src2))))]>;
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def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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"addsubps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
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VR128:$src2))]>;
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def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"addsubps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
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(loadv4f32 addr:$src2)))]>;
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def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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"addsubpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
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VR128:$src2))]>;
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def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"addsubpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
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(loadv2f64 addr:$src2)))]>;
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}
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def SQRTPSr : PS_Intr<0x51, "sqrtps {$src, $dst|$dst, $src}",
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@ -1300,21 +1370,21 @@ def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
|
||||
|
||||
// Horizontal ops
|
||||
let isTwoAddress = 1 in {
|
||||
def HADDPSrr : S3S_Intrr<0x7C, "haddps {$src2, $dst|$dst, $src2}",
|
||||
def HADDPSrr : S3D_Intrr<0x7C, "haddps {$src2, $dst|$dst, $src2}",
|
||||
int_x86_sse3_hadd_ps>;
|
||||
def HADDPSrm : S3S_Intrm<0x7C, "haddps {$src2, $dst|$dst, $src2}",
|
||||
def HADDPSrm : S3D_Intrm<0x7C, "haddps {$src2, $dst|$dst, $src2}",
|
||||
int_x86_sse3_hadd_ps>;
|
||||
def HADDPDrr : S3D_Intrr<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
|
||||
def HADDPDrr : S3_Intrr<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
|
||||
int_x86_sse3_hadd_pd>;
|
||||
def HADDPDrm : S3D_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
|
||||
def HADDPDrm : S3_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
|
||||
int_x86_sse3_hadd_pd>;
|
||||
def HSUBPSrr : S3S_Intrr<0x7C, "hsubps {$src2, $dst|$dst, $src2}",
|
||||
def HSUBPSrr : S3D_Intrr<0x7C, "hsubps {$src2, $dst|$dst, $src2}",
|
||||
int_x86_sse3_hsub_ps>;
|
||||
def HSUBPSrm : S3S_Intrm<0x7C, "hsubps {$src2, $dst|$dst, $src2}",
|
||||
def HSUBPSrm : S3D_Intrm<0x7C, "hsubps {$src2, $dst|$dst, $src2}",
|
||||
int_x86_sse3_hsub_ps>;
|
||||
def HSUBPDrr : S3D_Intrr<0x7C, "hsubpd {$src2, $dst|$dst, $src2}",
|
||||
def HSUBPDrr : S3_Intrr<0x7C, "hsubpd {$src2, $dst|$dst, $src2}",
|
||||
int_x86_sse3_hsub_pd>;
|
||||
def HSUBPDrm : S3D_Intrm<0x7C, "hsubpd {$src2, $dst|$dst, $src2}",
|
||||
def HSUBPDrm : S3_Intrm<0x7C, "hsubpd {$src2, $dst|$dst, $src2}",
|
||||
int_x86_sse3_hsub_pd>;
|
||||
}
|
||||
|
||||
@ -2023,6 +2093,14 @@ def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),
|
||||
"stmxcsr $dst",
|
||||
[(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>;
|
||||
|
||||
// Thread synchronization
|
||||
def MONITOR : I<0xC8, RawFrm, (ops), "monitor",
|
||||
[(int_x86_sse3_monitor EAX, ECX, EDX)]>,
|
||||
TB, Requires<[HasSSE3]>;
|
||||
def MWAIT : I<0xC9, RawFrm, (ops), "mwait",
|
||||
[(int_x86_sse3_mwait ECX, EAX)]>,
|
||||
TB, Requires<[HasSSE3]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Alias Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -2271,9 +2349,9 @@ def : Pat<(v16i8 (X86zexts2vec R8:$src)),
|
||||
(MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
|
||||
|
||||
// Splat v2f64 / v2i64
|
||||
def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_mask:$sm),
|
||||
def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
|
||||
(v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
|
||||
def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_mask:$sm),
|
||||
def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
|
||||
(v2i64 (PUNPCKLQDQrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
|
||||
|
||||
// Splat v4f32
|
||||
@ -2316,6 +2394,22 @@ def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
|
||||
UNPCKL_v_undef_shuffle_mask)),
|
||||
(PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
|
||||
|
||||
// vector_shuffle v1, <undef> <1, 1, 3, 3>
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
|
||||
MOVSHDUP_shuffle_mask)),
|
||||
(MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
|
||||
def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
|
||||
MOVSHDUP_shuffle_mask)),
|
||||
(MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
|
||||
|
||||
// vector_shuffle v1, <undef> <0, 0, 2, 2>
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
|
||||
MOVSLDUP_shuffle_mask)),
|
||||
(MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
|
||||
def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
|
||||
MOVSLDUP_shuffle_mask)),
|
||||
(MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
|
||||
|
||||
// 128-bit logical shifts
|
||||
def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
|
||||
(v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user