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Revert r116983, which is breaking all the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116987 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -331,28 +331,6 @@ def CortexA8Itineraries : ProcessorItineraries<
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InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<29, [A8_NPipe], 0>,
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InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
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//
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// Integer to Single-precision Move
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InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<1, [A8_NPipe]>],
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[2, 1]>,
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//
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// Integer to Double-precision Move
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InstrItinData<IIC_fpMOVID, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<1, [A8_NPipe]>],
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[2, 1, 1]>,
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//
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// Single-precision to Integer Move
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InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<1, [A8_NPipe]>],
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[20, 1]>,
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//
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// Double-precision to Integer Move
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InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<1, [A8_NPipe]>],
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[20, 20, 1]>,
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//
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// Single-precision FP Load
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InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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@ -641,7 +641,7 @@ def CortexA9Itineraries : ProcessorItineraries<
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InstrStage<1, [A9_DRegsVFP], 0, Required>,
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InstrStage<2, [A9_DRegsN], 0, Reserved>,
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InstrStage<1, [A9_NPipe]>],
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[2, 1]>,
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[1, 1]>,
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//
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// Double-precision to Integer Move
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InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
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@ -649,7 +649,7 @@ def CortexA9Itineraries : ProcessorItineraries<
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InstrStage<1, [A9_DRegsVFP], 0, Required>,
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InstrStage<2, [A9_DRegsN], 0, Reserved>,
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InstrStage<1, [A9_NPipe]>],
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[2, 1, 1]>,
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[1, 1, 1]>,
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//
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// Single-precision FP Load
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InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
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@ -1430,7 +1430,7 @@ def CortexA9Itineraries : ProcessorItineraries<
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InstrStage<1, [A9_DRegsN], 0, Required>,
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InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
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InstrStage<1, [A9_NPipe]>],
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[1, 1]>,
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[2, 1]>,
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//
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// Integer to Double-precision Move
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InstrItinData<IIC_VMOVID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
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@ -1438,7 +1438,7 @@ def CortexA9Itineraries : ProcessorItineraries<
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InstrStage<1, [A9_DRegsN], 0, Required>,
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InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
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InstrStage<1, [A9_NPipe]>],
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[1, 1, 1]>,
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[2, 1, 1]>,
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//
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// Single-precision to Integer Move
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InstrItinData<IIC_VMOVSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
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@ -247,18 +247,6 @@ def ARMV6Itineraries : ProcessorItineraries<
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// Double-precision FP SQRT
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InstrItinData<IIC_fpSQRT64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>,
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//
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// Integer to Single-precision Move
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InstrItinData<IIC_fpMOVIS, [InstrStage<1, [V6_Pipe]>], [10, 1]>,
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//
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// Integer to Double-precision Move
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InstrItinData<IIC_fpMOVID, [InstrStage<1, [V6_Pipe]>], [10, 1, 1]>,
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//
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// Single-precision to Integer Move
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InstrItinData<IIC_fpMOVSI, [InstrStage<1, [V6_Pipe]>], [10, 1]>,
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//
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// Double-precision to Integer Move
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InstrItinData<IIC_fpMOVDI, [InstrStage<1, [V6_Pipe]>], [10, 10, 1]>,
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//
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// Single-precision FP Load
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InstrItinData<IIC_fpLoad32 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>,
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//
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@ -19,6 +19,6 @@ entry:
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; NFP0: vnmls.f32 s2, s1, s0
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; CORTEXA8: test:
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; CORTEXA8: vnmls.f32 s1, s2, s0
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; CORTEXA8: vnmls.f32 s2, s1, s0
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; CORTEXA9: test:
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; CORTEXA9: vnmls.f32 s0, s1, s2
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@ -75,8 +75,7 @@ define <8 x i8> @t3(i8* %A, i8* %B) nounwind {
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; CHECK: t3:
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; CHECK: vld3.8
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; CHECK: vmul.i8
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; CHECK: vmov r
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; CHECK-NOT: vmov d
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; CHECK-NOT: vmov
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; CHECK: vst3.8
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%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
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%tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1]
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