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Correctly load FP constants out of the constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14782 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1608,20 +1608,17 @@ void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
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MachineConstantPool *CP = F->getConstantPool();
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unsigned CPI = CP->getConstantPoolIndex(Op1C);
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const Type *Ty = Op1->getType();
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assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
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static const unsigned OpcodeTab[][4] = {
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{ PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
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{ PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
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};
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assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
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unsigned TempReg = makeAnotherReg(Ty);
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unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC32::LFS : PPC32::LFD;
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addConstantPoolReference(BuildMI(*BB, IP, LoadOpcode, 2, TempReg), CPI);
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unsigned Op1Reg = getReg(Op1C);
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unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
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unsigned Op0r = getReg(Op0, BB, IP);
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BuildMI(*BB, IP, Opcode, DestReg).addReg(Op0r).addReg(TempReg);
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BuildMI(*BB, IP, Opcode, DestReg).addReg(Op0r).addReg(Op1Reg);
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return;
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}
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@ -1608,20 +1608,17 @@ void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
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MachineConstantPool *CP = F->getConstantPool();
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unsigned CPI = CP->getConstantPoolIndex(Op1C);
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const Type *Ty = Op1->getType();
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assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
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static const unsigned OpcodeTab[][4] = {
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{ PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
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{ PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
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};
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assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
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unsigned TempReg = makeAnotherReg(Ty);
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unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC32::LFS : PPC32::LFD;
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addConstantPoolReference(BuildMI(*BB, IP, LoadOpcode, 2, TempReg), CPI);
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unsigned Op1Reg = getReg(Op1C);
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unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
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unsigned Op0r = getReg(Op0, BB, IP);
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BuildMI(*BB, IP, Opcode, DestReg).addReg(Op0r).addReg(TempReg);
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BuildMI(*BB, IP, Opcode, DestReg).addReg(Op0r).addReg(Op1Reg);
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return;
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}
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