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Remove the TRI::getSubRegisterRegClass() hook.
This restores my karma after I added TRI::getSubClassWithSubReg(). Register constraints are applied 'backwards'. Starting from the register class required by an instruction operand, the correct question is: 'How can I constrain the super-register register class so all its sub-registers satisfy the instruction constraint?' The getMatchingSuperRegClass() hook answers that. We never need to go 'forwards': Starting from a super-register register class, what register class are the sub-registers in? The getSubRegisterRegClass() hook did that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141258 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -42,16 +42,14 @@ private:
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const vt_iterator VTs;
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const vt_iterator VTs;
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const unsigned *SubClassMask;
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const unsigned *SubClassMask;
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const sc_iterator SuperClasses;
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const sc_iterator SuperClasses;
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const sc_iterator SubRegClasses;
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const sc_iterator SuperRegClasses;
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const sc_iterator SuperRegClasses;
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public:
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public:
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TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts,
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TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts,
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const unsigned *subcm,
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const unsigned *subcm,
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const TargetRegisterClass * const *supcs,
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const TargetRegisterClass * const *supcs,
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const TargetRegisterClass * const *subregcs,
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const TargetRegisterClass * const *superregcs)
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const TargetRegisterClass * const *superregcs)
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: MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs),
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: MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs),
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SubRegClasses(subregcs), SuperRegClasses(superregcs) {}
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SuperRegClasses(superregcs) {}
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virtual ~TargetRegisterClass() {} // Allow subclasses
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virtual ~TargetRegisterClass() {} // Allow subclasses
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@ -127,25 +125,6 @@ public:
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return I;
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return I;
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}
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}
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/// subregclasses_begin / subregclasses_end - Loop over all of
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/// the subreg register classes of this register class.
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sc_iterator subregclasses_begin() const {
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return SubRegClasses;
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}
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sc_iterator subregclasses_end() const {
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sc_iterator I = SubRegClasses;
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while (*I != NULL) ++I;
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return I;
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}
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/// getSubRegisterRegClass - Return the register class of subregisters with
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/// index SubIdx, or NULL if no such class exists.
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const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
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assert(SubIdx>0 && "Invalid subregister index");
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return SubRegClasses[SubIdx-1];
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}
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/// superregclasses_begin / superregclasses_end - Loop over all of
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/// superregclasses_begin / superregclasses_end - Loop over all of
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/// the superreg register classes of this register class.
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/// the superreg register classes of this register class.
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sc_iterator superregclasses_begin() const {
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sc_iterator superregclasses_begin() const {
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@ -543,40 +543,17 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
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unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
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if (NumSubRegIndices) {
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if (NumSubRegIndices) {
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// Emit the sub-register classes for each RegisterClass
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// Compute the super-register classes for each RegisterClass
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = *RegisterClasses[rc];
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const CodeGenRegisterClass &RC = *RegisterClasses[rc];
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std::vector<Record*> SRC(NumSubRegIndices);
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for (DenseMap<Record*,Record*>::const_iterator
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for (DenseMap<Record*,Record*>::const_iterator
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i = RC.SubRegClasses.begin(),
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i = RC.SubRegClasses.begin(),
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e = RC.SubRegClasses.end(); i != e; ++i) {
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e = RC.SubRegClasses.end(); i != e; ++i) {
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// Build SRC array.
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unsigned idx = RegBank.getSubRegIndexNo(i->first);
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SRC.at(idx-1) = i->second;
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// Find the register class number of i->second for SuperRegClassMap.
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// Find the register class number of i->second for SuperRegClassMap.
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const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
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const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
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assert(RC2 && "Invalid register class in SubRegClasses");
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assert(RC2 && "Invalid register class in SubRegClasses");
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SuperRegClassMap[RC2->EnumValue].insert(rc);
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SuperRegClassMap[RC2->EnumValue].insert(rc);
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}
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}
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.getName();
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OS << " // " << Name
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<< " Sub-register Classes...\n"
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<< " static const TargetRegisterClass* const "
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<< Name << "SubRegClasses[] = {\n ";
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for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
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if (idx)
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OS << ", ";
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if (SRC[idx])
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OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
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else
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OS << "0";
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}
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OS << "\n };\n\n";
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}
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}
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// Emit the super-register classes for each RegisterClass
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// Emit the super-register classes for each RegisterClass
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@ -651,9 +628,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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OS << "NullRegClasses, ";
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OS << "NullRegClasses, ";
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else
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else
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OS << RC.getName() + "Superclasses, ";
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OS << RC.getName() + "Superclasses, ";
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OS << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
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OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
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<< "RegClasses, "
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<< (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
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<< "RegClasses"
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<< "RegClasses"
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<< ") {}\n";
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<< ") {}\n";
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if (!RC.AltOrderSelect.empty()) {
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if (!RC.AltOrderSelect.empty()) {
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