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Fix a typo in a comment that Gabor noticed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104711 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -449,7 +449,7 @@ def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
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[(set GR32:$dst, (int_x86_sse_cvtss2si
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(load addr:$src)))]>;
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// Match intrinisics which expect MM and XMM operand(s).
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// Match intrinsics which expect MM and XMM operand(s).
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def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
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"cvtps2pi\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
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@ -1277,7 +1277,7 @@ def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
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[(set GR32:$dst, (int_x86_sse2_cvtsd2si
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(load addr:$src)))]>;
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// Match intrinisics which expect MM and XMM operand(s).
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// Match intrinsics which expect MM and XMM operand(s).
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def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
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"cvtpd2pi\t{$src, $dst|$dst, $src}",
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[(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
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@ -2460,7 +2460,7 @@ def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
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"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
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// Pause. This "instruction" is encoded as "rep; nop", so even though it
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// was introduced with SSE2, it's backward compabitle.
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// was introduced with SSE2, it's backward compatible.
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def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
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//TODO: custom lower this so as to never even generate the noop
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