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Fix optimisations of SELECT_CC which assumed result is boolean
Some optimisations in DAGCombiner cause miscompilations for targets that use TargetLowering::UndefinedBooleanContent, because they assume that the results of a SELECT_CC node are boolean values, and can be safely ANDed, ORed and XORed. These optimisations are only valid for targets that use ZeroOrOneBooleanContent or ZeroOrNegativeOneBooleanContent. This is a follow-up to D6210/r221693. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222123 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -645,6 +645,10 @@ bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
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!TLI.isConstFalseVal(N.getOperand(3).getNode()))
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return false;
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if (TLI.getBooleanContents(N.getValueType()) ==
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TargetLowering::UndefinedBooleanContent)
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return false;
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LHS = N.getOperand(0);
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RHS = N.getOperand(1);
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CC = N.getOperand(4);
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@ -3826,8 +3830,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
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return RXOR;
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// fold !(x cc y) -> (x !cc y)
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if (N1C && N1C->getAPIntValue().isAllOnesValue() &&
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isSetCCEquivalent(N0, LHS, RHS, CC)) {
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if (TLI.isConstTrueVal(N1.getNode()) && isSetCCEquivalent(N0, LHS, RHS, CC)) {
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bool isInt = LHS.getValueType().isInteger();
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ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
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isInt);
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@ -224,18 +224,108 @@ entry:
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}
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; Do not fold the xor into the select
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define i32 @t15(i32 %p1, i32 %p2, i32 %p3) {
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define i32 @t15(i32 %p) {
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entry:
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; ARM: cmp r0, #8
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; ARM: mov{{(le|gt)}} [[REG:r[0-9]+]], {{r[0-9]+}}
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; ARM: eor r0, [[REG]], #1
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; ARM-LABEL: t15:
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; ARM: mov [[REG:r[0-9]+]], #2
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; ARM: cmp r0, #8
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; ARM: movwgt [[REG:r[0-9]+]], #1
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; ARM: eor r0, [[REG:r[0-9]+]], #1
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; T2: cmp r0, #8
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; T2: it [[CC:(le|gt)]]
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; T2: mov[[CC]] [[REG:r[0-9]+]], {{r[0-9]+}}
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; T2: eor r0, [[REG:r[0-9]+]], #1
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%cmp = icmp sgt i32 %p1, 8
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%a = select i1 %cmp, i32 %p2, i32 %p3
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; T2-LABEL: t15:
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; T2: movs [[REG:r[0-9]+]], #2
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; T2: cmp [[REG:r[0-9]+]], #8
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; T2: it gt
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; T2: movgt [[REG:r[0-9]+]], #1
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; T2: eor r0, [[REG:r[0-9]+]], #1
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%cmp = icmp sgt i32 %p, 8
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%a = select i1 %cmp, i32 1, i32 2
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%xor = xor i32 %a, 1
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ret i32 %xor
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}
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define i32 @t16(i32 %x, i32 %y) {
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entry:
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; ARM-LABEL: t16:
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; ARM: and r0, {{r[0-9]+}}, {{r[0-9]+}}
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; T2-LABEL: t16:
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; T2: ands r0, {{r[0-9]+}}
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%cmp = icmp eq i32 %x, 0
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%cond = select i1 %cmp, i32 5, i32 2
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%cmp1 = icmp eq i32 %y, 0
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%cond2 = select i1 %cmp1, i32 3, i32 4
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%and = and i32 %cond2, %cond
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ret i32 %and
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}
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define i32 @t17(i32 %x, i32 %y) #0 {
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entry:
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; ARM-LABEL: t17:
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; ARM: and r0, {{r[0-9]+}}, {{r[0-9]+}}
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; T2-LABEL: t17:
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; T2: ands r0, {{r[0-9]+}}
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%cmp = icmp eq i32 %x, -1
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%cond = select i1 %cmp, i32 5, i32 2
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%cmp1 = icmp eq i32 %y, -1
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%cond2 = select i1 %cmp1, i32 3, i32 4
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%and = and i32 %cond2, %cond
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ret i32 %and
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}
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define i32 @t18(i32 %x, i32 %y) #0 {
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entry:
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; ARM-LABEL: t18:
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; ARM: and r0, {{r[0-9]+}}, {{r[0-9]+}}
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; T2-LABEL: t18:
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; T2: and.w r0, {{r[0-9]+}}
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%cmp = icmp ne i32 %x, 0
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%cond = select i1 %cmp, i32 5, i32 2
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%cmp1 = icmp ne i32 %x, -1
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%cond2 = select i1 %cmp1, i32 3, i32 4
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%and = and i32 %cond2, %cond
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ret i32 %and
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}
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define i32 @t19(i32 %x, i32 %y) #0 {
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entry:
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; ARM-LABEL: t19:
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; ARM: orr r0, {{r[0-9]+}}, {{r[0-9]+}}
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; T2-LABEL: t19:
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; T2: orrs r0, {{r[0-9]+}}
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%cmp = icmp ne i32 %x, 0
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%cond = select i1 %cmp, i32 5, i32 2
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%cmp1 = icmp ne i32 %y, 0
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%cond2 = select i1 %cmp1, i32 3, i32 4
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%or = or i32 %cond2, %cond
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ret i32 %or
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}
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define i32 @t20(i32 %x, i32 %y) #0 {
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entry:
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; ARM-LABEL: t20:
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; ARM: orr r0, {{r[0-9]+}}, {{r[0-9]+}}
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; T2-LABEL: t20:
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; T2: orrs r0, {{r[0-9]+}}
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%cmp = icmp ne i32 %x, -1
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%cond = select i1 %cmp, i32 5, i32 2
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%cmp1 = icmp ne i32 %y, -1
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%cond2 = select i1 %cmp1, i32 3, i32 4
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%or = or i32 %cond2, %cond
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ret i32 %or
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}
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define <2 x i32> @t21(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK-LABEL: t21:
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; CHECK-NOT: eor
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; CHECK: mvn
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; CHECK-NOT: eor
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%tst = icmp eq <2 x i32> %lhs, %rhs
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%ntst = xor <2 x i1> %tst, <i1 1 , i1 undef>
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%btst = sext <2 x i1> %ntst to <2 x i32>
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ret <2 x i32> %btst
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}
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