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Use i32 for all SPARC shift amounts, even in 64-bit mode.

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Test case by llvm-stress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179477 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2013-04-14 05:48:50 +00:00
parent 1f098af364
commit d9f88da7b3
5 changed files with 18 additions and 7 deletions
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4
lib/Target/Sparc/SparcISelLowering.cpp
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@ -1415,7 +1415,7 @@ SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
case CodeModel::Medium: {
// abs44.
SDValue H44 = makeHiLoPair(Op, SPII::MO_H44, SPII::MO_M44, DAG);
H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getIntPtrConstant(12));
H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32));
SDValue L44 = withTargetFlags(Op, SPII::MO_L44, DAG);
L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
@ -1423,7 +1423,7 @@ SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
case CodeModel::Large: {
// abs64.
SDValue Hi = makeHiLoPair(Op, SPII::MO_HH, SPII::MO_HM, DAG);
Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getIntPtrConstant(32));
Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32));
SDValue Lo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
}

1
lib/Target/Sparc/SparcISelLowering.h
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@ -71,6 +71,7 @@ namespace llvm {
getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
virtual SDValue
LowerFormalArguments(SDValue Chain,

2
lib/Target/Sparc/SparcInstr64Bit.td
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@ -133,7 +133,7 @@ def HM10 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(Val, MVT::i32);
}]>;
def : Pat<(i64 imm:$val),
(ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i64 32)),
(ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)),
(ORri (SETHIi (HI22 $val)), (LO10 $val)))>,
Requires<[Is64Bit]>;

8
lib/Target/Sparc/SparcInstrFormats.td
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@ -142,10 +142,10 @@ class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
// Define rr and ri shift instructions with patterns.
multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
ValueType VT, RegisterClass RC> {
def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, RC:$rs2),
def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, IntRegs:$rs2),
!strconcat(OpcStr, " $rs, $rs2, $rd"),
[(set VT:$rd, (OpNode VT:$rs, VT:$rs2))]>;
def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, unknown:$shcnt),
[(set VT:$rd, (OpNode VT:$rs, i32:$rs2))]>;
def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, i32imm:$shcnt),
!strconcat(OpcStr, " $rs, $shcnt, $rd"),
[(set VT:$rd, (OpNode VT:$rs, (VT imm:$shcnt)))]>;
[(set VT:$rd, (OpNode VT:$rs, (i32 imm:$shcnt)))]>;
}

10
test/CodeGen/SPARC/64bit.ll
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@ -144,3 +144,13 @@ define void @stores(i64* %p, i32* %q, i16* %r, i8* %s) {
ret void
}
; CHECK: promote_shifts
; CHECK: ldub [%i0], [[R:%[goli][0-7]]]
; CHECK: sll [[R]], [[R]], %i0
define i8 @promote_shifts(i8* %p) {
%L24 = load i8* %p
%L32 = load i8* %p
%B36 = shl i8 %L24, %L32
ret i8 %B36
}