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PEI: refactor replaceFrameIndices(MF) to call replaceFrameIndices(BB).
replaceFrameIndices(MF) will iterate over the BBs and call replaceFrameIndices(BB). No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186141 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -728,6 +728,14 @@ void PEI::insertPrologEpilogCode(MachineFunction &Fn) {
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void PEI::replaceFrameIndices(MachineFunction &Fn) {
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if (!Fn.getFrameInfo()->hasStackObjects()) return; // Nothing to do?
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for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
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int SPAdj = 0;
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replaceFrameIndices(BB, Fn, SPAdj);
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}
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}
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void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn,
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int &SPAdj) {
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const TargetMachine &TM = Fn.getTarget();
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assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
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const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
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@ -738,105 +746,101 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) {
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int FrameSetupOpcode = TII.getCallFrameSetupOpcode();
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int FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
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for (MachineFunction::iterator BB = Fn.begin(),
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E = Fn.end(); BB != E; ++BB) {
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#ifndef NDEBUG
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int SPAdjCount = 0; // frame setup / destroy count.
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int SPAdjCount = 0; // frame setup / destroy count.
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#endif
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int SPAdj = 0; // SP offset due to call frame setup / destroy.
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if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(BB);
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if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(BB);
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for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ) {
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for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ) {
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if (I->getOpcode() == FrameSetupOpcode ||
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I->getOpcode() == FrameDestroyOpcode) {
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if (I->getOpcode() == FrameSetupOpcode ||
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I->getOpcode() == FrameDestroyOpcode) {
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#ifndef NDEBUG
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// Track whether we see even pairs of them
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SPAdjCount += I->getOpcode() == FrameSetupOpcode ? 1 : -1;
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// Track whether we see even pairs of them
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SPAdjCount += I->getOpcode() == FrameSetupOpcode ? 1 : -1;
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#endif
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// Remember how much SP has been adjusted to create the call
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// frame.
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int Size = I->getOperand(0).getImm();
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// Remember how much SP has been adjusted to create the call
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// frame.
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int Size = I->getOperand(0).getImm();
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if ((!StackGrowsDown && I->getOpcode() == FrameSetupOpcode) ||
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(StackGrowsDown && I->getOpcode() == FrameDestroyOpcode))
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Size = -Size;
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if ((!StackGrowsDown && I->getOpcode() == FrameSetupOpcode) ||
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(StackGrowsDown && I->getOpcode() == FrameDestroyOpcode))
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Size = -Size;
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SPAdj += Size;
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SPAdj += Size;
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MachineBasicBlock::iterator PrevI = BB->end();
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if (I != BB->begin()) PrevI = prior(I);
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TFI->eliminateCallFramePseudoInstr(Fn, *BB, I);
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MachineBasicBlock::iterator PrevI = BB->end();
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if (I != BB->begin()) PrevI = prior(I);
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TFI->eliminateCallFramePseudoInstr(Fn, *BB, I);
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// Visit the instructions created by eliminateCallFramePseudoInstr().
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if (PrevI == BB->end())
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I = BB->begin(); // The replaced instr was the first in the block.
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else
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I = llvm::next(PrevI);
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// Visit the instructions created by eliminateCallFramePseudoInstr().
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if (PrevI == BB->end())
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I = BB->begin(); // The replaced instr was the first in the block.
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else
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I = llvm::next(PrevI);
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continue;
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}
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MachineInstr *MI = I;
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bool DoIncr = true;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if (!MI->getOperand(i).isFI())
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continue;
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// Frame indicies in debug values are encoded in a target independent
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// way with simply the frame index and offset rather than any
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// target-specific addressing mode.
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if (MI->isDebugValue()) {
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assert(i == 0 && "Frame indicies can only appear as the first "
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"operand of a DBG_VALUE machine instruction");
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unsigned Reg;
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MachineOperand &Offset = MI->getOperand(1);
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Offset.setImm(Offset.getImm() +
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TFI->getFrameIndexReference(
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Fn, MI->getOperand(0).getIndex(), Reg));
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MI->getOperand(0).ChangeToRegister(Reg, false /*isDef*/);
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continue;
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}
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MachineInstr *MI = I;
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bool DoIncr = true;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if (!MI->getOperand(i).isFI())
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continue;
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// Some instructions (e.g. inline asm instructions) can have
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// multiple frame indices and/or cause eliminateFrameIndex
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// to insert more than one instruction. We need the register
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// scavenger to go through all of these instructions so that
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// it can update its register information. We keep the
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// iterator at the point before insertion so that we can
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// revisit them in full.
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bool AtBeginning = (I == BB->begin());
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if (!AtBeginning) --I;
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// Frame indicies in debug values are encoded in a target independent
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// way with simply the frame index and offset rather than any
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// target-specific addressing mode.
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if (MI->isDebugValue()) {
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assert(i == 0 && "Frame indicies can only appear as the first "
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"operand of a DBG_VALUE machine instruction");
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unsigned Reg;
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MachineOperand &Offset = MI->getOperand(1);
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Offset.setImm(Offset.getImm() +
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TFI->getFrameIndexReference(
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Fn, MI->getOperand(0).getIndex(), Reg));
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MI->getOperand(0).ChangeToRegister(Reg, false /*isDef*/);
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continue;
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}
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// If this instruction has a FrameIndex operand, we need to
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// use that target machine register info object to eliminate
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// it.
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TRI.eliminateFrameIndex(MI, SPAdj, i,
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FrameIndexVirtualScavenging ? NULL : RS);
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// Some instructions (e.g. inline asm instructions) can have
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// multiple frame indices and/or cause eliminateFrameIndex
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// to insert more than one instruction. We need the register
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// scavenger to go through all of these instructions so that
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// it can update its register information. We keep the
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// iterator at the point before insertion so that we can
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// revisit them in full.
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bool AtBeginning = (I == BB->begin());
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if (!AtBeginning) --I;
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// If this instruction has a FrameIndex operand, we need to
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// use that target machine register info object to eliminate
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// it.
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TRI.eliminateFrameIndex(MI, SPAdj, i,
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FrameIndexVirtualScavenging ? NULL : RS);
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// Reset the iterator if we were at the beginning of the BB.
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if (AtBeginning) {
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I = BB->begin();
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DoIncr = false;
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}
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MI = 0;
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break;
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// Reset the iterator if we were at the beginning of the BB.
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if (AtBeginning) {
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I = BB->begin();
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DoIncr = false;
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}
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if (DoIncr && I != BB->end()) ++I;
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// Update register states.
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if (RS && !FrameIndexVirtualScavenging && MI) RS->forward(MI);
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MI = 0;
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break;
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}
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// If we have evenly matched pairs of frame setup / destroy instructions,
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// make sure the adjustments come out to zero. If we don't have matched
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// pairs, we can't be sure the missing bit isn't in another basic block
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// due to a custom inserter playing tricks, so just asserting SPAdj==0
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// isn't sufficient. See tMOVCC on Thumb1, for example.
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assert((SPAdjCount || SPAdj == 0) &&
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"Unbalanced call frame setup / destroy pairs?");
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if (DoIncr && I != BB->end()) ++I;
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// Update register states.
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if (RS && !FrameIndexVirtualScavenging && MI) RS->forward(MI);
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}
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// If we have evenly matched pairs of frame setup / destroy instructions,
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// make sure the adjustments come out to zero. If we don't have matched
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// pairs, we can't be sure the missing bit isn't in another basic block
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// due to a custom inserter playing tricks, so just asserting SPAdj==0
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// isn't sufficient. See tMOVCC on Thumb1, for example.
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assert((SPAdjCount || SPAdj == 0) &&
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"Unbalanced call frame setup / destroy pairs?");
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}
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/// scavengeFrameVirtualRegs - Replace all frame index virtual registers
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@ -127,6 +127,8 @@ namespace llvm {
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void insertCSRSpillsAndRestores(MachineFunction &Fn);
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void calculateFrameObjectOffsets(MachineFunction &Fn);
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void replaceFrameIndices(MachineFunction &Fn);
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void replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn,
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int &SPAdj);
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void scavengeFrameVirtualRegs(MachineFunction &Fn);
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void insertPrologEpilogCode(MachineFunction &Fn);
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