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SelectionDAG: Use correct pointer size when lowering function arguments v2

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This adds minimal support to the SelectionDAG for handling address spaces
with different pointer sizes.  The SelectionDAG should now correctly
lower pointer function arguments to the correct size as well as generate
the correct code when lowering getelementptr.

This patch also updates the R600 DataLayout to use 32-bit pointers for
the local address space.

v2:
  - Add more helper functions to TargetLoweringBase
  - Use CHECK-LABEL for tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189221 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-08-26 15:05:36 +00:00
parent b51439594a
commit da25cd3e6d
8 changed files with 79 additions and 14 deletions
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6
include/llvm/Target/TargetLowering.h
View File

@ -151,7 +151,9 @@ public:
// Return the pointer type for the given address space, defaults to
// the pointer type from the data layout.
// FIXME: The default needs to be removed once all the code is updated.
virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const { return PointerTy; }
virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
unsigned getPointerSizeInBits(uint32_t AS = 0) const;
unsigned getPointerTypeSizeInBits(Type *Ty) const;
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
EVT getShiftAmountTy(EVT LHSTy) const;
@ -568,7 +570,7 @@ public:
/// otherwise it will assert.
EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
// Lower scalar pointers to native pointer types.
if (Ty->isPointerTy()) return PointerTy;
if (Ty->isPointerTy()) return getPointerTy(Ty->getPointerAddressSpace());
if (Ty->isVectorTy()) {
VectorType *VTy = cast<VectorType>(Ty);

13
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -3242,6 +3242,10 @@ void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
Ty = StTy->getElementType(Field);
} else {
uint32_t AS = 0;
if (PointerType *PtrType = dyn_cast<PointerType>(Ty)) {
AS = PtrType->getAddressSpace();
}
Ty = cast<SequentialType>(Ty)->getElementType();
// If this is a constant subscript, handle it quickly.
@ -3251,14 +3255,13 @@ void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
uint64_t Offs =
TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
SDValue OffsVal;
EVT PTy = TLI->getPointerTy();
EVT PTy = TLI->getPointerTy(AS);
unsigned PtrBits = PTy.getSizeInBits();
if (PtrBits < 64)
OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(),
TLI->getPointerTy(),
OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
DAG.getConstant(Offs, MVT::i64));
else
OffsVal = DAG.getIntPtrConstant(Offs);
OffsVal = DAG.getConstant(Offs, PTy);
N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
OffsVal);
@ -3266,7 +3269,7 @@ void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
}
// N = N + Idx * ElementSize;
APInt ElementSize = APInt(TLI->getPointerTy().getSizeInBits(),
APInt ElementSize = APInt(TLI->getPointerSizeInBits(AS),
TD->getTypeAllocSize(Ty));
SDValue IdxN = getValue(Idx);

13
lib/CodeGen/TargetLoweringBase.cpp
View File

@ -767,6 +767,19 @@ void TargetLoweringBase::initActions() {
setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
}
MVT TargetLoweringBase::getPointerTy(uint32_t AS) const {
return MVT::getIntegerVT(getPointerSizeInBits(AS));
}
unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const {
return TD->getPointerSizeInBits(AS);
}
unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const {
assert(Ty->isPointerTy());
return getPointerSizeInBits(Ty->getPointerAddressSpace());
}
MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const {
return MVT::getIntegerVT(8*TD->getPointerSize(0));
}

4
lib/Target/R600/AMDGPUISelLowering.cpp
View File

@ -233,6 +233,8 @@ SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
const DataLayout *TD = getTargetMachine().getDataLayout();
GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
assert(G->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS);
// XXX: What does the value of G->getOffset() mean?
assert(G->getOffset() == 0 &&
"Do not know what to do with an non-zero offset");
@ -244,7 +246,7 @@ SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
// XXX: Account for alignment?
MFI->LDSSize += Size;
return DAG.getConstant(Offset, TD->getPointerSize() == 8 ? MVT::i64 : MVT::i32);
return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
}
void AMDGPUTargetLowering::ExtractVectorElements(SDValue Op, SelectionDAG &DAG,

4
lib/Target/R600/AMDGPUSubtarget.cpp
View File

@ -97,6 +97,10 @@ AMDGPUSubtarget::getDataLayout() const {
DataLayout.append("-p:32:32:32");
}
if (Gen >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
DataLayout.append("-p3:32:32:32");
}
return DataLayout;
}

2
lib/Target/R600/SIISelLowering.cpp
View File

@ -87,7 +87,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setTargetDAGCombine(ISD::SELECT_CC);

9
lib/Target/R600/SIInstructions.td
View File

@ -1746,14 +1746,13 @@ def : Pat <
/********** ======================= **********/
def : Pat <
(local_load i64:$src0),
(i32 (DS_READ_B32 0, (EXTRACT_SUBREG $src0, sub0),
(EXTRACT_SUBREG $src0, sub0), (EXTRACT_SUBREG $src0, sub0), 0, 0))
(local_load i32:$src0),
(i32 (DS_READ_B32 0, $src0, $src0, $src0, 0, 0))
>;
def : Pat <
(local_store i32:$src1, i64:$src0),
(DS_WRITE_B32 0, (EXTRACT_SUBREG $src0, sub0), $src1, $src1, 0, 0)
(local_store i32:$src1, i32:$src0),
(DS_WRITE_B32 0, $src0, $src1, $src1, 0, 0)
>;
/********** ================== **********/

42
test/CodeGen/R600/32-bit-local-address-space.ll Normal file
View File

@ -0,0 +1,42 @@
; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and
; the global address space(1) uses 64-bit pointers. These tests check to make sure
; the correct pointer size is used for the local address space.
; The e{{32|64}} suffix on the instructions refers to the encoding size and not
; the size of the operands. The operand size is denoted in the instruction name.
; Instructions with B32, U32, and I32 in their name take 32-bit operands, while
; instructions with B64, U64, and I64 take 64-bit operands.
; CHECK-LABEL: @local_address_load
; CHECK: V_MOV_B32_e{{32|64}} [[PTR:VGPR[0-9]]]
; CHECK: DS_READ_B32 [[PTR]]
define void @local_address_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
entry:
%0 = load i32 addrspace(3)* %in
store i32 %0, i32 addrspace(1)* %out
ret void
}
; CHECK-LABEL: @local_address_gep
; CHECK: V_ADD_I32_e{{32|64}} [[PTR:VGPR[0-9]]]
; CHECK: DS_READ_B32 [[PTR]]
define void @local_address_gep(i32 addrspace(1)* %out, i32 addrspace(3)* %in, i32 %offset) {
entry:
%0 = getelementptr i32 addrspace(3)* %in, i32 %offset
%1 = load i32 addrspace(3)* %0
store i32 %1, i32 addrspace(1)* %out
ret void
}
; CHECK-LABEL: @local_address_gep_const_offset
; CHECK: V_ADD_I32_e{{32|64}} [[PTR:VGPR[0-9]]]
; CHECK: DS_READ_B32 [[PTR]]
define void @local_address_gep_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
entry:
%0 = getelementptr i32 addrspace(3)* %in, i32 1
%1 = load i32 addrspace(3)* %0
store i32 %1, i32 addrspace(1)* %out
ret void
}