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* Adjust to changes in TargetLowering interfaces.
* Remove custom promotion for bool and byte select ops. Legalize now promotes them for us. * Allow folding ConstantPoolIndexes into EXTLOAD's, useful for float immediates. * Declare which operations are not supported better. * Add some hacky code for TRUNCSTORE to pretend that we have truncstore for i16 types. This is useful for testing promotion code because I can just remove 16-bit registers all together and verify that programs work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19614 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -46,16 +46,23 @@ namespace {
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// FIXME: Eliminate these two classes when legalize can handle promotions
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// well.
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addRegisterClass(MVT::i1, X86::R8RegisterClass);
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addRegisterClass(MVT::f32, X86::RFPRegisterClass);
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/**/ addRegisterClass(MVT::i1, X86::R8RegisterClass);
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/**/ //addRegisterClass(MVT::f32, X86::RFPRegisterClass);
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setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
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setOperationAction(ISD::ZERO_EXTEND_INREG, MVT::i16 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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setOperationAction(ISD::ZERO_EXTEND_INREG, MVT::i1 , Expand);
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setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::SREM , MVT::f64 , Expand);
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// These should be promoted to a larger select which is supported.
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/**/ setOperationAction(ISD::SELECT , MVT::i1 , Promote);
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setOperationAction(ISD::SELECT , MVT::i8 , Promote);
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computeRegisterProperties();
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setOperationUnsupported(ISD::MEMMOVE, MVT::Other);
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//setOperationUnsupported(ISD::SEXTLOAD, MVT::i1);
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setOperationUnsupported(ISD::SELECT, MVT::i1);
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setOperationUnsupported(ISD::SELECT, MVT::i8);
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addLegalFPImmediate(+0.0); // FLD0
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addLegalFPImmediate(+1.0); // FLD1
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@ -1698,42 +1705,23 @@ unsigned ISel::SelectExpr(SDOperand N) {
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return Result;
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}
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case ISD::SELECT:
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if (N.getValueType() != MVT::i1 && N.getValueType() != MVT::i8) {
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if (getRegPressure(N.getOperand(1)) > getRegPressure(N.getOperand(2))) {
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Tmp2 = SelectExpr(N.getOperand(1));
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Tmp3 = SelectExpr(N.getOperand(2));
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} else {
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Tmp3 = SelectExpr(N.getOperand(2));
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Tmp2 = SelectExpr(N.getOperand(1));
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}
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EmitSelectCC(N.getOperand(0), N.getValueType(), Tmp2, Tmp3, Result);
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return Result;
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if (getRegPressure(N.getOperand(1)) > getRegPressure(N.getOperand(2))) {
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Tmp2 = SelectExpr(N.getOperand(1));
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Tmp3 = SelectExpr(N.getOperand(2));
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} else {
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// FIXME: This should not be implemented here, it should be in the generic
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// code!
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if (getRegPressure(N.getOperand(1)) > getRegPressure(N.getOperand(2))) {
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Tmp2 = SelectExpr(CurDAG->getNode(ISD::ZERO_EXTEND, MVT::i16,
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N.getOperand(1)));
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Tmp3 = SelectExpr(CurDAG->getNode(ISD::ZERO_EXTEND, MVT::i16,
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N.getOperand(2)));
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} else {
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Tmp3 = SelectExpr(CurDAG->getNode(ISD::ZERO_EXTEND, MVT::i16,
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N.getOperand(2)));
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Tmp2 = SelectExpr(CurDAG->getNode(ISD::ZERO_EXTEND, MVT::i16,
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N.getOperand(1)));
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}
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unsigned TmpReg = MakeReg(MVT::i16);
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EmitSelectCC(N.getOperand(0), MVT::i16, Tmp2, Tmp3, TmpReg);
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// FIXME: need subregs to do better than this!
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BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(TmpReg);
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BuildMI(BB, X86::MOV8rr, 1, Result).addReg(X86::AL);
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return Result;
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Tmp3 = SelectExpr(N.getOperand(2));
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Tmp2 = SelectExpr(N.getOperand(1));
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}
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EmitSelectCC(N.getOperand(0), N.getValueType(), Tmp2, Tmp3, Result);
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return Result;
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::SREM:
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case ISD::UREM: {
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assert((N.getOpcode() != ISD::SREM || MVT::isInteger(N.getValueType())) &&
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"We don't support this operator!");
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if (N.getOpcode() == ISD::SDIV)
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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// FIXME: These special cases should be handled by the lowering impl!
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@ -1823,10 +1811,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case MVT::i64: assert(0 && "FIXME: implement i64 DIV/REM libcalls!");
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case MVT::f32:
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case MVT::f64:
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if (N.getOpcode() == ISD::SDIV)
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BuildMI(BB, X86::FpDIV, 2, Result).addReg(Tmp1).addReg(Tmp2);
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else
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assert(0 && "FIXME: Emit frem libcall to fmod!");
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BuildMI(BB, X86::FpDIV, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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}
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@ -2002,6 +1987,15 @@ unsigned ISel::SelectExpr(SDOperand N) {
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(1)))
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if (Node->getValueType(0) == MVT::f64) {
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assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::f32 &&
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"Bad EXTLOAD!");
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addConstantPoolReference(BuildMI(BB, X86::FLD32m, 4, Result),
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CP->getIndex());
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return Result;
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}
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X86AddressMode AM;
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if (getRegPressure(Node->getOperand(0)) >
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getRegPressure(Node->getOperand(1))) {
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@ -2322,8 +2316,23 @@ void ISel::Select(SDOperand N) {
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// On X86, we can represent all types except for Bool and Float natively.
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X86AddressMode AM;
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MVT::ValueType StoredTy = cast<MVTSDNode>(Node)->getExtraValueType();
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assert((StoredTy == MVT::i1 || StoredTy == MVT::f32) &&
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"Unsupported TRUNCSTORE for this target!");
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assert((StoredTy == MVT::i1 || StoredTy == MVT::f32 ||
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StoredTy == MVT::i16 /*FIXME: THIS IS JUST FOR TESTING!*/)
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&& "Unsupported TRUNCSTORE for this target!");
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if (StoredTy == MVT::i16) {
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// FIXME: This is here just to allow testing. X86 doesn't really have a
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// TRUNCSTORE i16 operation, but this is required for targets that do not
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// have 16-bit integer registers. We occasionally disable 16-bit integer
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// registers to test the promotion code.
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Select(N.getOperand(0));
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Tmp1 = SelectExpr(N.getOperand(1));
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SelectAddress(N.getOperand(2), AM);
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BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(Tmp1);
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addFullAddress(BuildMI(BB, X86::MOV16mr, 5), AM).addReg(X86::AX);
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return;
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}
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// Store of constant bool?
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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