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Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
b7994fedcb
commit
da394041c4
@ -100,6 +100,8 @@ def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
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"Support MOVBE instruction">;
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def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true",
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"Support RDRAND instruction">;
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def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
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"Support 16-bit floating point conversion instructions">;
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//===----------------------------------------------------------------------===//
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// X86 processors supported.
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@ -475,6 +475,7 @@ def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
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def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
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def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
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def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
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def HasF16C : Predicate<"Subtarget->hasF16C()">;
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def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
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def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
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def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
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@ -6753,9 +6753,39 @@ let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
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YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
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// Zero All YMM registers
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def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
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[(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
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[(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
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// Zero Upper bits of YMM registers
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def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
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[(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
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}
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//===----------------------------------------------------------------------===//
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// Half precision conversion instructions
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//
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let Predicates = [HasF16C] in {
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def VCVTPH2PSrm : I<0x13, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
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"vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
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def VCVTPH2PSrr : I<0x13, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
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def VCVTPH2PSYrm : I<0x13, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
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"vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
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def VCVTPH2PSYrr : I<0x13, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
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"vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
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def VCVTPS2PHmr : Ii8<0x1D, MRMDestMem, (outs f64mem:$dst),
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(ins VR128:$src1, i32i8imm:$src2),
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"vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
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TA, OpSize, VEX;
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def VCVTPS2PHrr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
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(ins VR128:$src1, i32i8imm:$src2),
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"vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
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TA, OpSize, VEX;
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def VCVTPS2PHYmr : Ii8<0x1D, MRMDestMem, (outs f128mem:$dst),
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(ins VR256:$src1, i32i8imm:$src2),
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"vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
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TA, OpSize, VEX;
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def VCVTPS2PHYrr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
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(ins VR256:$src1, i32i8imm:$src2),
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"vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
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TA, OpSize, VEX;
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}
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@ -206,6 +206,7 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
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HasMOVBE = IsIntel && ((ECX >> 22) & 0x1); ToggleFeature(X86::FeatureMOVBE);
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HasPOPCNT = IsIntel && ((ECX >> 23) & 0x1); ToggleFeature(X86::FeaturePOPCNT);
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HasAES = IsIntel && ((ECX >> 25) & 0x1); ToggleFeature(X86::FeatureAES);
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HasF16C = IsIntel && ((ECX >> 29) & 0x1); ToggleFeature(X86::FeatureF16C);
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HasRDRAND = IsIntel && ((ECX >> 30) & 0x1); ToggleFeature(X86::FeatureRDRAND);
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HasCmpxchg16b = ((ECX >> 13) & 0x1); ToggleFeature(X86::FeatureCMPXCHG16B);
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@ -258,6 +259,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
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, HasFMA4(false)
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, HasMOVBE(false)
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, HasRDRAND(false)
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, HasF16C(false)
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, IsBTMemSlow(false)
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, IsUAMemFast(false)
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, HasVectorUAMem(false)
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@ -90,12 +90,15 @@ protected:
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/// HasFMA4 - Target has 4-operand fused multiply-add
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bool HasFMA4;
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/// HasMOVBE - True if the processor has the MOVBE instruction;
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/// HasMOVBE - True if the processor has the MOVBE instruction.
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bool HasMOVBE;
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/// HasRDRAND - True if the processor has the RDRAND instruction;
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/// HasRDRAND - True if the processor has the RDRAND instruction.
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bool HasRDRAND;
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/// HasF16C - Processor has 16-bit floating point conversion instructions.
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bool HasF16C;
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/// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
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bool IsBTMemSlow;
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@ -180,6 +183,7 @@ public:
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bool hasFMA4() const { return HasFMA4; }
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bool hasMOVBE() const { return HasMOVBE; }
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bool hasRDRAND() const { return HasRDRAND; }
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bool hasF16C() const { return HasF16C; }
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bool isBTMemSlow() const { return IsBTMemSlow; }
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bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
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bool hasVectorUAMem() const { return HasVectorUAMem; }
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@ -432,26 +432,50 @@
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# CHECK: xsaveopt (%rax)
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0x0f 0xae 0x30
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# CHECK rdfsbasel %eax
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# CHECK: rdfsbasel %eax
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0xf3 0x0f 0xae 0xc0
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# CHECK rdgsbasel %eax
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# CHECK: rdgsbasel %eax
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0xf3 0x0f 0xae 0xc8
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# CHECK wrfsbasel %eax
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# CHECK: wrfsbasel %eax
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0xf3 0x0f 0xae 0xd0
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# CHECK wrgsbasel %eax
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# CHECK: wrgsbasel %eax
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0xf3 0x0f 0xae 0xd8
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# CHECK rdfsbaseq %rax
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# CHECK: rdfsbaseq %rax
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0xf3 0x48 0x0f 0xae 0xc0
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# CHECK rdgsbaseq %rax
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# CHECK: rdgsbaseq %rax
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0xf3 0x48 0x0f 0xae 0xc8
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# CHECK wrfsbaseq %rax
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# CHECK: wrfsbaseq %rax
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0xf3 0x48 0x0f 0xae 0xd0
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# CHECK wrgsbaseq %rax
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# CHECK: wrgsbaseq %rax
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0xf3 0x48 0x0f 0xae 0xd8
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# CHECK: vcvtph2ps %xmm0, %xmm0
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0xc4 0xe2 0x79 0x13 0xc0
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# CHECK: vcvtph2ps (%rax), %xmm0
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0xc4 0xe2 0x79 0x13 0x00
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# CHECK: vcvtph2ps %xmm0, %ymm0
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0xc4 0xe2 0x7d 0x13 0xc0
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# CHECK: vcvtph2ps (%rax), %ymm0
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0xc4 0xe2 0x7d 0x13 0x00
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# CHECK: vcvtps2ph $0, %xmm0, %xmm0
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0xc4 0xe3 0x79 0x1d 0xc0 0x00
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# CHECK: vcvtps2ph $0, %xmm0, (%rax)
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0xc4 0xe3 0x79 0x1d 0x00 0x00
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# CHECK: vcvtps2ph $0, %ymm0, %xmm0
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0xc4 0xe3 0x7d 0x1d 0xc0 0x00
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# CHECK: vcvtps2ph $0, %ymm0, (%rax)
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0xc4 0xe3 0x7d 0x1d 0x00 0x00
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@ -441,3 +441,27 @@
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# CHECK: xsaveopt (%eax)
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0x0f 0xae 0x30
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# CHECK: vcvtph2ps %xmm0, %xmm0
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0xc4 0xe2 0x79 0x13 0xc0
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# CHECK: vcvtph2ps (%eax), %xmm0
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0xc4 0xe2 0x79 0x13 0x00
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# CHECK: vcvtph2ps %xmm0, %ymm0
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0xc4 0xe2 0x7d 0x13 0xc0
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# CHECK: vcvtph2ps (%eax), %ymm0
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0xc4 0xe2 0x7d 0x13 0x00
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# CHECK: vcvtps2ph $0, %xmm0, %xmm0
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0xc4 0xe3 0x79 0x1d 0xc0 0x00
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# CHECK: vcvtps2ph $0, %xmm0, (%eax)
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0xc4 0xe3 0x79 0x1d 0x00 0x00
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# CHECK: vcvtps2ph $0, %ymm0, %xmm0
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0xc4 0xe3 0x7d 0x1d 0xc0 0x00
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# CHECK: vcvtps2ph $0, %ymm0, (%eax)
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0xc4 0xe3 0x7d 0x1d 0x00 0x00
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