From da3a8a647d6be9510b363ef574656c535d52475d Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 28 Apr 2010 01:53:13 +0000 Subject: [PATCH] Update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102487 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/rot16.ll | 22 +++++++++++++++++----- test/CodeGen/X86/rot32.ll | 22 +++++++++++++++++----- test/CodeGen/X86/shl_elim.ll | 2 +- 3 files changed, 35 insertions(+), 11 deletions(-) diff --git a/test/CodeGen/X86/rot16.ll b/test/CodeGen/X86/rot16.ll index 42ece47b030..de23dcb78f1 100644 --- a/test/CodeGen/X86/rot16.ll +++ b/test/CodeGen/X86/rot16.ll @@ -1,11 +1,9 @@ -; RUN: llc < %s -march=x86 > %t -; RUN: grep rol %t | count 3 -; RUN: grep ror %t | count 1 -; RUN: grep shld %t | count 2 -; RUN: grep shrd %t | count 2 +; RUN: llc < %s -march=x86 | FileCheck %s define i16 @foo(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: foo: +; CHECK: rolw %cl %0 = shl i16 %x, %z %1 = sub i16 16, %z %2 = lshr i16 %x, %1 @@ -15,6 +13,8 @@ entry: define i16 @bar(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: bar: +; CHECK: shldw %cl %0 = shl i16 %y, %z %1 = sub i16 16, %z %2 = lshr i16 %x, %1 @@ -24,6 +24,8 @@ entry: define i16 @un(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: un: +; CHECK: rorw %cl %0 = lshr i16 %x, %z %1 = sub i16 16, %z %2 = shl i16 %x, %1 @@ -33,6 +35,8 @@ entry: define i16 @bu(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: bu: +; CHECK: shrdw %0 = lshr i16 %y, %z %1 = sub i16 16, %z %2 = shl i16 %x, %1 @@ -42,6 +46,8 @@ entry: define i16 @xfoo(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: xfoo: +; CHECK: rolw $5 %0 = lshr i16 %x, 11 %1 = shl i16 %x, 5 %2 = or i16 %0, %1 @@ -50,6 +56,8 @@ entry: define i16 @xbar(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: xbar: +; CHECK: shldw $5 %0 = shl i16 %y, 5 %1 = lshr i16 %x, 11 %2 = or i16 %0, %1 @@ -58,6 +66,8 @@ entry: define i16 @xun(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: xun: +; CHECK: rolw $11 %0 = lshr i16 %x, 5 %1 = shl i16 %x, 11 %2 = or i16 %0, %1 @@ -66,6 +76,8 @@ entry: define i16 @xbu(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: xbu: +; CHECK: shldw $11 %0 = lshr i16 %y, 5 %1 = shl i16 %x, 11 %2 = or i16 %0, %1 diff --git a/test/CodeGen/X86/rot32.ll b/test/CodeGen/X86/rot32.ll index 655ed272837..99602fd64ff 100644 --- a/test/CodeGen/X86/rot32.ll +++ b/test/CodeGen/X86/rot32.ll @@ -1,11 +1,9 @@ -; RUN: llc < %s -march=x86 > %t -; RUN: grep rol %t | count 3 -; RUN: grep ror %t | count 1 -; RUN: grep shld %t | count 2 -; RUN: grep shrd %t | count 2 +; RUN: llc < %s -march=x86 | FileCheck %s define i32 @foo(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: foo: +; CHECK: roll %cl %0 = shl i32 %x, %z %1 = sub i32 32, %z %2 = lshr i32 %x, %1 @@ -15,6 +13,8 @@ entry: define i32 @bar(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: bar: +; CHECK: shldl %cl %0 = shl i32 %y, %z %1 = sub i32 32, %z %2 = lshr i32 %x, %1 @@ -24,6 +24,8 @@ entry: define i32 @un(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: un: +; CHECK: rorl %cl %0 = lshr i32 %x, %z %1 = sub i32 32, %z %2 = shl i32 %x, %1 @@ -33,6 +35,8 @@ entry: define i32 @bu(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: bu: +; CHECK: shrdl %cl %0 = lshr i32 %y, %z %1 = sub i32 32, %z %2 = shl i32 %x, %1 @@ -42,6 +46,8 @@ entry: define i32 @xfoo(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: xfoo: +; CHECK: roll $7 %0 = lshr i32 %x, 25 %1 = shl i32 %x, 7 %2 = or i32 %0, %1 @@ -50,6 +56,8 @@ entry: define i32 @xbar(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: xbar: +; CHECK: shldl $7 %0 = shl i32 %y, 7 %1 = lshr i32 %x, 25 %2 = or i32 %0, %1 @@ -58,6 +66,8 @@ entry: define i32 @xun(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: xun: +; CHECK: roll $25 %0 = lshr i32 %x, 7 %1 = shl i32 %x, 25 %2 = or i32 %0, %1 @@ -66,6 +76,8 @@ entry: define i32 @xbu(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: xbu: +; CHECK: shldl %0 = lshr i32 %y, 7 %1 = shl i32 %x, 25 %2 = or i32 %0, %1 diff --git a/test/CodeGen/X86/shl_elim.ll b/test/CodeGen/X86/shl_elim.ll index 445889166bd..0827221875b 100644 --- a/test/CodeGen/X86/shl_elim.ll +++ b/test/CodeGen/X86/shl_elim.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -march=x86 | grep {shrl .eax} ; RUN: llc < %s -march=x86 | grep {movswl .ax, .eax} -define i32 @test1(i64 %a) { +define i32 @test1(i64 %a) nounwind { %tmp29 = lshr i64 %a, 24 ; [#uses=1] %tmp23 = trunc i64 %tmp29 to i32 ; [#uses=1] %tmp410 = lshr i32 %tmp23, 9 ; [#uses=1]