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Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56526 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1169,9 +1169,11 @@ public:
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/// type to use for the specific AsmOperandInfo, setting
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/// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
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/// being passed in is available, it can be passed in as Op, otherwise an
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/// empty SDValue can be passed.
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/// empty SDValue can be passed. If hasMemory is true it means one of the asm
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/// constraint of the inline asm instruction being processed is 'm'.
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virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
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SDValue Op,
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bool hasMemory,
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SelectionDAG *DAG = 0) const;
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/// getConstraintType - Given a constraint, return the type of constraint it
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@ -1206,8 +1208,11 @@ public:
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virtual const char *LowerXConstraint(MVT ConstraintVT) const;
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops.
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/// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
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/// it means one of the asm constraint of the inline asm instruction being
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/// processed is 'm'.
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virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
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bool hasMemory,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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@ -4629,6 +4629,22 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
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// Otherwise, we couldn't allocate enough registers for this.
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}
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/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
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/// processed uses a memory 'm' constraint.
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static bool
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hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
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TargetLowering &TLI) {
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for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
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InlineAsm::ConstraintInfo &CI = CInfos[i];
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for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
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TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
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if (CType == TargetLowering::C_Memory)
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return true;
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}
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}
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return false;
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}
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/// visitInlineAsm - Handle a call to an InlineAsm object.
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///
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@ -4652,6 +4668,8 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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// constraint. If so, we can't let the register allocator allocate any input
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// registers, because it will not know to avoid the earlyclobbered output reg.
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bool SawEarlyClobber = false;
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bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
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unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
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unsigned ResNo = 0; // ResNo - The result number of the next output.
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@ -4724,7 +4742,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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OpInfo.ConstraintVT = OpVT;
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// Compute the constraint code and ConstraintType to use.
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TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
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TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
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// Keep track of whether we see an earlyclobber.
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SawEarlyClobber |= OpInfo.isEarlyClobber;
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@ -4927,7 +4945,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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std::vector<SDValue> Ops;
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TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
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Ops, DAG);
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hasMemory, Ops, DAG);
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if (Ops.empty()) {
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cerr << "Invalid operand for inline asm constraint '"
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<< OpInfo.ConstraintCode << "'!\n";
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@ -1855,6 +1855,7 @@ const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{
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/// vector. If it is invalid, don't add anything to Ops.
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void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
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char ConstraintLetter,
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bool hasMemory,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const {
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switch (ConstraintLetter) {
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@ -1997,7 +1998,7 @@ static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
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/// 'm' over 'r', for example.
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///
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static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
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const TargetLowering &TLI,
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bool hasMemory, const TargetLowering &TLI,
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SDValue Op, SelectionDAG *DAG) {
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assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
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unsigned BestIdx = 0;
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@ -2017,7 +2018,7 @@ static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
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assert(OpInfo.Codes[i].size() == 1 &&
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"Unhandled multi-letter 'other' constraint");
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std::vector<SDValue> ResultOps;
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TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0],
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TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
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ResultOps, *DAG);
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if (!ResultOps.empty()) {
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BestType = CType;
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@ -2044,6 +2045,7 @@ static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
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/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
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void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
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SDValue Op,
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bool hasMemory,
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SelectionDAG *DAG) const {
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assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
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@ -2052,7 +2054,7 @@ void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
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OpInfo.ConstraintCode = OpInfo.Codes[0];
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OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
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} else {
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ChooseConstraint(OpInfo, *this, Op, DAG);
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ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
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}
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// 'X' matches anything.
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@ -3040,10 +3040,12 @@ SPUTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
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void
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SPUTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
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char ConstraintLetter,
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bool hasMemory,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const {
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// Default, for the time being, to the base class handler
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TargetLowering::LowerAsmOperandForConstraint(Op, ConstraintLetter, Ops, DAG);
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TargetLowering::LowerAsmOperandForConstraint(Op, ConstraintLetter, hasMemory,
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Ops, DAG);
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}
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/// isLegalAddressImmediate - Return true if the integer value can be used
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@ -131,6 +131,7 @@ namespace llvm {
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MVT VT) const;
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void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
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bool hasMemory,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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@ -4763,8 +4763,11 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops.
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/// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
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/// it means one of the asm constraint of the inline asm instruction being
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/// processed is 'm'.
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void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
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bool hasMemory,
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std::vector<SDValue>&Ops,
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SelectionDAG &DAG) const {
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SDValue Result(0,0);
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@ -4823,7 +4826,7 @@ void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
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}
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// Handle standard constraint letters.
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TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
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TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG);
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}
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// isLegalAddressingMode - Return true if the addressing mode represented
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@ -300,9 +300,12 @@ namespace llvm {
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unsigned getByValTypeAlignment(const Type *Ty) const;
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops.
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/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
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/// true it means one of the asm constraint of the inline asm instruction
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/// being processed is 'm'.
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virtual void LowerAsmOperandForConstraint(SDValue Op,
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char ConstraintLetter,
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bool hasMemory,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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@ -767,7 +767,7 @@ void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
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/// addressing mode.
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bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
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bool isRoot, unsigned Depth) {
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DOUT << "MatchAddress: "; DEBUG(AM.dump());
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DOUT << "MatchAddress: "; DEBUG(AM.dump());
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// Limit recursion.
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if (Depth > 5)
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return MatchAddressBase(N, AM, isRoot, Depth);
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@ -1593,7 +1593,7 @@ SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
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if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
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// Note: The actual moving to ecx is done further down.
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GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
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if (G && !G->getGlobal()->hasHiddenVisibility() &&
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if (G && !G->getGlobal()->hasHiddenVisibility() &&
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!G->getGlobal()->hasProtectedVisibility())
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Callee = LowerGlobalAddress(Callee, DAG);
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else if (isa<ExternalSymbolSDNode>(Callee))
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@ -4300,8 +4300,8 @@ X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
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}
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SDValue
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X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
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GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV,
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SelectionDAG &DAG) const {
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SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
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Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
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// With PIC, the address is actually $g + Offset.
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@ -4324,6 +4324,12 @@ X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
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return Result;
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}
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SDValue
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X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
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const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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return LowerGlobalAddress(GV, DAG);
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}
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// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
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static SDValue
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LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
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@ -7067,6 +7073,7 @@ LowerXConstraint(MVT ConstraintVT) const {
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/// vector. If it is invalid, don't add anything to Ops.
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void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
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char Constraint,
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bool hasMemory,
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std::vector<SDValue>&Ops,
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SelectionDAG &DAG) const {
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SDValue Result(0, 0);
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@ -7128,14 +7135,11 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
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}
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if (GA) {
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// If addressing this global requires a load (e.g. in PIC mode), we can't
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// match.
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if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
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false))
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return;
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Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
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Offset);
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if (hasMemory)
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Op = LowerGlobalAddress(GA->getGlobal(), DAG);
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else
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Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
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Offset);
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Result = Op;
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break;
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}
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@ -7149,7 +7153,8 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
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Ops.push_back(Result);
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return;
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}
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return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
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return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
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Ops, DAG);
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}
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std::vector<unsigned> X86TargetLowering::
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@ -403,9 +403,12 @@ namespace llvm {
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virtual const char *LowerXConstraint(MVT ConstraintVT) const;
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops.
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/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
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/// true it means one of the asm constraint of the inline asm instruction
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/// being processed is 'm'.
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virtual void LowerAsmOperandForConstraint(SDValue Op,
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char ConstraintLetter,
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bool hasMemory,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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@ -529,6 +532,7 @@ namespace llvm {
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SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
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SDValue LowerGlobalAddress(const GlobalValue *GV, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
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10
test/CodeGen/X86/inline-asm-pic.ll
Normal file
10
test/CodeGen/X86/inline-asm-pic.ll
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@ -0,0 +1,10 @@
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; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -relocation-model=pic | grep lea
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; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -relocation-model=pic | grep call
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@main_q = internal global i8* null ; <i8**> [#uses=1]
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define void @func2() nounwind {
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entry:
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tail call void asm "mov $1,%gs:$0", "=*m,ri,~{dirflag},~{fpsr},~{flags}"(i8** inttoptr (i32 152 to i8**), i8* bitcast (i8** @main_q to i8*)) nounwind
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ret void
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}
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