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Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-03-15 00:03:38 +00:00
parent af59b105bb
commit da47e6e0d0
31 changed files with 68 additions and 178 deletions
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8
include/llvm/CodeGen/AsmPrinter.h
View File

@ -66,6 +66,10 @@ namespace llvm {
///
const TargetAsmInfo *TAI;
/// Target Register Information.
///
const TargetRegisterInfo *TRI;
/// Name-mangler for global names.
///
Mangler *Mang;
@ -319,6 +323,10 @@ namespace llvm {
/// instruction that is an inline asm.
void printInlineAsm(const MachineInstr *MI) const;
/// printImplicitDef - This method prints the specified machine instruction
/// that is an implicit def.
virtual void printImplicitDef(const MachineInstr *MI) const;
/// printBasicBlockLabel - This method prints the label for the specified
/// MachineBasicBlock
virtual void printBasicBlockLabel(const MachineBasicBlock *MBB,

3
include/llvm/Target/TargetInstrInfo.h
View File

@ -49,7 +49,8 @@ public:
LABEL = 2,
DECLARE = 3,
EXTRACT_SUBREG = 4,
INSERT_SUBREG = 5
INSERT_SUBREG = 5,
IMPLICIT_DEF = 6
};
// Target independent implict values for use with subreg insert. All targets

11
lib/CodeGen/AsmPrinter.cpp
View File

@ -29,6 +29,7 @@
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/SmallPtrSet.h"
#include <cerrno>
using namespace llvm;
@ -39,7 +40,8 @@ AsmVerbose("asm-verbose", cl::Hidden, cl::desc("Add comments to directives."));
char AsmPrinter::ID = 0;
AsmPrinter::AsmPrinter(std::ostream &o, TargetMachine &tm,
const TargetAsmInfo *T)
: MachineFunctionPass((intptr_t)&ID), FunctionNumber(0), O(o), TM(tm), TAI(T),
: MachineFunctionPass((intptr_t)&ID), FunctionNumber(0), O(o),
TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
IsInTextSection(false)
{}
@ -1294,6 +1296,13 @@ void AsmPrinter::printInlineAsm(const MachineInstr *MI) const {
O << "\n\t" << TAI->getInlineAsmEnd() << "\n";
}
/// printImplicitDef - This method prints the specified machine instruction
/// that is an implicit def.
void AsmPrinter::printImplicitDef(const MachineInstr *MI) const {
O << "\t" << TAI->getCommentString() << " implicit-def: "
<< TRI->getAsmName(MI->getOperand(0).getReg()) << "\n";
}
/// printLabel - This method prints a local label used by debug and
/// exception handling tables.
void AsmPrinter::printLabel(const MachineInstr *MI) const {

11
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -467,8 +467,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
assert(isNew && "Node emitted out of order - early");
}
void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
MachineInstr *MI,
void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
const TargetInstrDesc &II,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
for (unsigned i = 0; i < II.getNumDefs(); ++i) {
@ -494,7 +493,13 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
// Create the result registers for this node and add the result regs to
// the machine instruction.
if (VRBase == 0) {
const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
const TargetRegisterClass *RC;
if (Node->getTargetOpcode() == TargetInstrInfo::IMPLICIT_DEF)
// IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
// does not include operand register class info.
RC = DAG.getTargetLoweringInfo().getRegClassFor(Node->getValueType(0));
else
RC = getInstrOperandRegClass(TRI, TII, II, i);
assert(RC && "Isn't a register operand!");
VRBase = MRI.createVirtualRegister(RC);
MI->addOperand(MachineOperand::CreateReg(VRBase, true));

2
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -877,6 +877,8 @@ unsigned ARM::GetInstSize(MachineInstr *MI) {
return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
if (MI->getOpcode() == ARM::LABEL)
return 0;
if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
return 0;
assert(0 && "Unknown or unset size field for instr!");
break;
case ARMII::Size8Bytes: return 8; // Arm instruction x 2.

6
lib/Target/ARM/ARMInstrInfo.td
View File

@ -645,12 +645,6 @@ multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
//===----------------------------------------------------------------------===//
// Miscellaneous Instructions.
//
let isImplicitDef = 1 in
def IMPLICIT_DEF_GPR :
PseudoInst<(outs GPR:$rD), (ins pred:$p),
"@ IMPLICIT_DEF_GPR $rD",
[(set GPR:$rD, (undef))]>;
/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
/// the function. The first operand is the ID# for this instruction, the second

9
lib/Target/ARM/ARMInstrVFP.td
View File

@ -249,15 +249,6 @@ def FSQRTS : ASI<(outs SPR:$dst), (ins SPR:$a),
// FP <-> GPR Copies. Int <-> FP Conversions.
//
let isImplicitDef = 1 in {
def IMPLICIT_DEF_SPR : PseudoInst<(outs SPR:$rD), (ins pred:$p),
"@ IMPLICIT_DEF_SPR $rD",
[(set SPR:$rD, (undef))]>;
def IMPLICIT_DEF_DPR : PseudoInst<(outs DPR:$rD), (ins pred:$p),
"@ IMPLICIT_DEF_DPR $rD",
[(set DPR:$rD, (undef))]>;
}
def FMRS : ASI<(outs GPR:$dst), (ins SPR:$src),
"fmrs", " $dst, $src",
[(set GPR:$dst, (bitconvert SPR:$src))]>;

3
lib/Target/Alpha/AlphaCodeEmitter.cpp
View File

@ -95,9 +95,6 @@ void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
case Alpha::ALTENT:
case Alpha::PCLABEL:
case Alpha::MEMLABEL:
case Alpha::IDEF_I:
case Alpha::IDEF_F32:
case Alpha::IDEF_F64:
break; //skip these
}
}

9
lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -141,15 +141,6 @@ class CmpOpFrag<dag res> : PatFrag<(ops node:$R), res>;
//Pseudo ops for selection
let isImplicitDef = 1 in {
def IDEF_I : PseudoInstAlpha<(outs GPRC:$RA), (ins), ";#idef $RA",
[(set GPRC:$RA, (undef))], s_pseudo>;
def IDEF_F32 : PseudoInstAlpha<(outs F4RC:$RA), (ins), ";#idef $RA",
[(set F4RC:$RA, (undef))], s_pseudo>;
def IDEF_F64 : PseudoInstAlpha<(outs F8RC:$RA), (ins), ";#idef $RA",
[(set F8RC:$RA, (undef))], s_pseudo>;
}
def WTF : PseudoInstAlpha<(outs), (ins variable_ops), "#wtf", [], s_pseudo>;
let hasCtrlDep = 1, Defs = [R30], Uses = [R30] in {

3
lib/Target/Alpha/AlphaLLRP.cpp
View File

@ -120,9 +120,6 @@ namespace {
case Alpha::ALTENT:
case Alpha::MEMLABEL:
case Alpha::PCLABEL:
case Alpha::IDEF_I:
case Alpha::IDEF_F32:
case Alpha::IDEF_F64:
--count;
break;
case Alpha::BR:

11
lib/Target/IA64/IA64InstrInfo.td
View File

@ -456,17 +456,6 @@ def : Pat<(i1 0), (CMPNE r0, r0)>; // TODO: any instruction actually *using*
// TODO: support postincrement (reg, imm9) loads+stores - this needs more
// tablegen support
let isImplicitDef = 1 in {
def IDEF : PseudoInstIA64<(outs variable_ops), (ins), "// IDEF">;
def IDEF_GR_D : PseudoInstIA64_DAG<(outs GR:$reg), (ins), "// $reg = IDEF",
[(set GR:$reg, (undef))]>;
def IDEF_FP_D : PseudoInstIA64_DAG<(outs FP:$reg), (ins), "// $reg = IDEF",
[(set FP:$reg, (undef))]>;
def IDEF_PR_D : PseudoInstIA64_DAG<(outs PR:$reg), (ins), "// $reg = IDEF",
[(set PR:$reg, (undef))]>;
}
def IUSE : PseudoInstIA64<(outs), (ins variable_ops), "// IUSE">;
def ADJUSTCALLSTACKUP : PseudoInstIA64<(outs), (ins variable_ops),
"// ADJUSTCALLSTACKUP">;

5
lib/Target/Mips/MipsInstrInfo.td
View File

@ -355,11 +355,6 @@ def ADJCALLSTACKUP : PseudoInstMips<(outs), (ins uimm16:$amt1, uimm16:$amt2),
[(callseq_end imm:$amt1, imm:$amt2)]>;
}
let isImplicitDef = 1 in
def IMPLICIT_DEF_CPURegs : PseudoInstMips<(outs CPURegs:$dst), (ins),
"!IMPLICIT_DEF $dst",
[(set CPURegs:$dst, (undef))]>;
// When handling PIC code the assembler needs .cpload and .cprestore
// directives. If the real instructions corresponding these directives
// are used, we have the same behavior, but get also a bunch of warnings

6
lib/Target/PowerPC/PPCBranchSelector.cpp
View File

@ -59,12 +59,6 @@ FunctionPass *llvm::createPPCBranchSelectionPass() {
///
static unsigned getNumBytesForInstruction(MachineInstr *MI) {
switch (MI->getOpcode()) {
case PPC::IMPLICIT_DEF_GPRC: // no asm emitted
case PPC::IMPLICIT_DEF_G8RC: // no asm emitted
case PPC::IMPLICIT_DEF_F4: // no asm emitted
case PPC::IMPLICIT_DEF_F8: // no asm emitted
case PPC::IMPLICIT_DEF_VRRC: // no asm emitted
return 0;
case PPC::INLINEASM: { // Inline Asm: Variable size.
MachineFunction *MF = MI->getParent()->getParent();
const char *AsmStr = MI->getOperand(0).getSymbolName();

6
lib/Target/PowerPC/PPCCodeEmitter.cpp
View File

@ -112,12 +112,6 @@ void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
case TargetInstrInfo::LABEL:
MCE.emitLabel(MI.getOperand(0).getImm());
break;
case PPC::IMPLICIT_DEF_GPRC:
case PPC::IMPLICIT_DEF_G8RC:
case PPC::IMPLICIT_DEF_F8:
case PPC::IMPLICIT_DEF_F4:
case PPC::IMPLICIT_DEF_VRRC:
break; // pseudo opcode, no side effects
case PPC::MovePCtoLR:
case PPC::MovePCtoLR8:
assert(TM.getRelocationModel() == Reloc::PIC_);

8
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -53,14 +53,6 @@ def HI48_64 : SDNodeXForm<imm, [{
}]>;
//===----------------------------------------------------------------------===//
// Pseudo instructions.
//
def IMPLICIT_DEF_G8RC : Pseudo<(outs G8RC:$rD), (ins),"; IMPLICIT_DEF_G8RC $rD",
[(set G8RC:$rD, (undef))]>;
//===----------------------------------------------------------------------===//
// Calls.
//

8
lib/Target/PowerPC/PPCInstrAltivec.td
View File

@ -160,9 +160,6 @@ class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
//===----------------------------------------------------------------------===//
// Instruction Definitions.
def IMPLICIT_DEF_VRRC : Pseudo<(outs VRRC:$rD), (ins),"; IMPLICIT_DEF_VRRC $rD",
[(set VRRC:$rD, (v4i32 (undef)))]>;
def DSS : DSS_Form<822, (outs),
(ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
"dss $STRM", LdStGeneral /*FIXME*/, []>;
@ -579,11 +576,6 @@ def : Pat<(int_ppc_altivec_dstst G8RC:$rA, GPRC:$rB, imm:$STRM),
def : Pat<(int_ppc_altivec_dststt G8RC:$rA, GPRC:$rB, imm:$STRM),
(DSTSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>;
// Undef.
def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VRRC)>;
def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VRRC)>;
def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VRRC)>;
// Loads.
def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;

12
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -335,18 +335,6 @@ def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
[(set GPRC:$result,
(PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
let isImplicitDef = 1 in {
def IMPLICIT_DEF_GPRC: Pseudo<(outs GPRC:$rD), (ins),
"${:comment}IMPLICIT_DEF_GPRC $rD",
[(set GPRC:$rD, (undef))]>;
def IMPLICIT_DEF_F8 : Pseudo<(outs F8RC:$rD), (ins),
"${:comment} IMPLICIT_DEF_F8 $rD",
[(set F8RC:$rD, (undef))]>;
def IMPLICIT_DEF_F4 : Pseudo<(outs F4RC:$rD), (ins),
"${:comment} IMPLICIT_DEF_F4 $rD",
[(set F4RC:$rD, (undef))]>;
}
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
// scheduler into a branch sequence.
let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.

10
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -212,16 +212,6 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
[(callseq_end imm:$amt1, imm:$amt2)]>;
}
let isImplicitDef = 1 in {
def IMPLICIT_DEF_Int : Pseudo<(outs IntRegs:$dst), (ins),
"!IMPLICIT_DEF $dst",
[(set IntRegs:$dst, (undef))]>;
def IMPLICIT_DEF_FP : Pseudo<(outs FPRegs:$dst), (ins), "!IMPLICIT_DEF $dst",
[(set FPRegs:$dst, (undef))]>;
def IMPLICIT_DEF_DFP : Pseudo<(outs DFPRegs:$dst), (ins), "!IMPLICIT_DEF $dst",
[(set DFPRegs:$dst, (undef))]>;
}
// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
// fpmover pass.
let Predicates = [HasNoV9] in { // Only emit these in V8 mode.

7
lib/Target/Target.td
View File

@ -368,6 +368,13 @@ def INSERT_SUBREG : Instruction {
let Namespace = "TargetInstrInfo";
let neverHasSideEffects = 1;
}
def IMPLICIT_DEF : Instruction {
let OutOperandList = (ops unknown:$dst);
let InOperandList = (ops);
let AsmString = "";
let Namespace = "TargetInstrInfo";
let neverHasSideEffects = 1;
}
//===----------------------------------------------------------------------===//
// AsmWriter - This class can be implemented by targets that need to customize

6
lib/Target/X86/X86ATTAsmPrinter.cpp
View File

@ -205,7 +205,6 @@ static inline bool printStub(TargetMachine &TM, const X86Subtarget* ST) {
void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
const char *Modifier, bool NotRIPRel) {
const MachineOperand &MO = MI->getOperand(OpNo);
const TargetRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_Register: {
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
@ -218,7 +217,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
for (const char *Name = RI.get(Reg).AsmName; *Name; ++Name)
for (const char *Name = TRI->getAsmName(Reg); *Name; ++Name)
O << (char)tolower(*Name);
return;
}
@ -548,7 +547,6 @@ void X86ATTAsmPrinter::printPICJumpTableEntry(const MachineJumpTableInfo *MJTI,
bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO,
const char Mode) {
const TargetRegisterInfo &RI = *TM.getRegisterInfo();
unsigned Reg = MO.getReg();
switch (Mode) {
default: return true; // Unknown mode.
@ -570,7 +568,7 @@ bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO,
}
O << '%';
for (const char *Name = RI.get(Reg).AsmName; *Name; ++Name)
for (const char *Name = TRI->getAsmName(Reg); *Name; ++Name)
O << (char)tolower(*Name);
return false;
}

8
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -623,14 +623,6 @@ void Emitter::emitInstruction(const MachineInstr &MI,
break;
case TargetInstrInfo::DECLARE:
case X86::DWARF_LOC:
case X86::IMPLICIT_DEF_GR8:
case X86::IMPLICIT_DEF_GR16:
case X86::IMPLICIT_DEF_GR32:
case X86::IMPLICIT_DEF_GR64:
case X86::IMPLICIT_DEF_FR32:
case X86::IMPLICIT_DEF_FR64:
case X86::IMPLICIT_DEF_VR64:
case X86::IMPLICIT_DEF_VR128:
case X86::FP_REG_KILL:
break;
case X86::MOVPC32r: {

5
lib/Target/X86/X86Instr64bit.td
View File

@ -86,11 +86,6 @@ def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
// Instruction list...
//
let isImplicitDef = 1 in
def IMPLICIT_DEF_GR64 : I<0, Pseudo, (outs GR64:$dst), (ins),
"#IMPLICIT_DEF $dst",
[(set GR64:$dst, (undef))]>;
//===----------------------------------------------------------------------===//
// Call Instructions...
//

11
lib/Target/X86/X86InstrInfo.td
View File

@ -279,17 +279,6 @@ def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
"#ADJCALLSTACKUP",
[(X86callseq_end imm:$amt1, imm:$amt2)]>;
}
let isImplicitDef = 1 in {
def IMPLICIT_DEF_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins),
"#IMPLICIT_DEF $dst",
[(set GR8:$dst, (undef))]>;
def IMPLICIT_DEF_GR16 : I<0, Pseudo, (outs GR16:$dst), (ins),
"#IMPLICIT_DEF $dst",
[(set GR16:$dst, (undef))]>;
def IMPLICIT_DEF_GR32 : I<0, Pseudo, (outs GR32:$dst), (ins),
"#IMPLICIT_DEF $dst",
[(set GR32:$dst, (undef))]>;
}
// Nop
let neverHasSideEffects = 1 in

13
lib/Target/X86/X86InstrMMX.td
View File

@ -13,19 +13,6 @@
//
//===----------------------------------------------------------------------===//
// Some 'special' instructions
let isImplicitDef = 1 in
def IMPLICIT_DEF_VR64 : I<0, Pseudo, (outs VR64:$dst), (ins),
"#IMPLICIT_DEF $dst",
[(set VR64:$dst, (v8i8 (undef)))]>,
Requires<[HasMMX]>;
// 64-bit vector undef's.
def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>;
def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>;
def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
def : Pat<(v1i64 (undef)), (IMPLICIT_DEF_VR64)>;
//===----------------------------------------------------------------------===//
// MMX Pattern Fragments
//===----------------------------------------------------------------------===//

25
lib/Target/X86/X86InstrSSE.td
View File

@ -48,23 +48,6 @@ def X86insrtps : SDNode<"X86ISD::INSERTPS",
SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
//===----------------------------------------------------------------------===//
// SSE 'Special' Instructions
//===----------------------------------------------------------------------===//
let isImplicitDef = 1 in {
def IMPLICIT_DEF_VR128 : I<0, Pseudo, (outs VR128:$dst), (ins),
"#IMPLICIT_DEF $dst",
[(set VR128:$dst, (v4f32 (undef)))]>,
Requires<[HasSSE1]>;
def IMPLICIT_DEF_FR32 : I<0, Pseudo, (outs FR32:$dst), (ins),
"#IMPLICIT_DEF $dst",
[(set FR32:$dst, (undef))]>, Requires<[HasSSE1]>;
def IMPLICIT_DEF_FR64 : I<0, Pseudo, (outs FR64:$dst), (ins),
"#IMPLICIT_DEF $dst",
[(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
}
//===----------------------------------------------------------------------===//
// SSE Complex Patterns
//===----------------------------------------------------------------------===//
@ -2754,14 +2737,6 @@ let Constraints = "$src1 = $dst" in {
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//
// 128-bit vector undef's.
def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
// extload f32 -> f64. This matches load+fextend because we have a hack in
// the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
// Since these loads aren't folded into the fextend, we have to match it

6
lib/Target/X86/X86IntelAsmPrinter.cpp
View File

@ -114,7 +114,6 @@ void X86IntelAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
const char *Modifier) {
const TargetRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_Register: {
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
@ -125,7 +124,7 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
O << RI.get(Reg).AsmName;
O << TRI->getAsmName(Reg);
} else
O << "reg" << MO.getReg();
return;
@ -253,7 +252,6 @@ void X86IntelAsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) {
bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO,
const char Mode) {
const TargetRegisterInfo &RI = *TM.getRegisterInfo();
unsigned Reg = MO.getReg();
switch (Mode) {
default: return true; // Unknown mode.
@ -271,7 +269,7 @@ bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO,
break;
}
O << '%' << RI.get(Reg).AsmName;
O << '%' << TRI->getAsmName(Reg);
return false;
}

3
utils/TableGen/AsmWriterEmitter.cpp
View File

@ -630,6 +630,9 @@ void AsmWriterEmitter::run(std::ostream &O) {
<< " } else if (MI->getOpcode() == TargetInstrInfo::DECLARE) {\n"
<< " printDeclare(MI);\n"
<< " return true;\n"
<< " } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {\n"
<< " printImplicitDef(MI);\n"
<< " return true;\n"
<< " }\n\n";
O << " O << \"\\t\";\n\n";

9
utils/TableGen/CodeEmitterGen.cpp
View File

@ -29,7 +29,8 @@ void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
R->getName() == "LABEL" ||
R->getName() == "DECLARE" ||
R->getName() == "EXTRACT_SUBREG" ||
R->getName() == "INSERT_SUBREG") continue;
R->getName() == "INSERT_SUBREG" ||
R->getName() == "IMPLICIT_DEF") continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
@ -103,7 +104,8 @@ void CodeEmitterGen::run(std::ostream &o) {
R->getName() == "LABEL" ||
R->getName() == "DECLARE" ||
R->getName() == "EXTRACT_SUBREG" ||
R->getName() == "INSERT_SUBREG") {
R->getName() == "INSERT_SUBREG" ||
R->getName() == "IMPLICIT_DEF") {
o << " 0U";
continue;
}
@ -136,7 +138,8 @@ void CodeEmitterGen::run(std::ostream &o) {
InstName == "LABEL"||
InstName == "DECLARE"||
InstName == "EXTRACT_SUBREG" ||
InstName == "INSERT_SUBREG") continue;
InstName == "INSERT_SUBREG" ||
InstName == "IMPLICIT_DEF") continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
const std::vector<RecordVal> &Vals = R->getValues();

9
utils/TableGen/CodeGenTarget.cpp
View File

@ -304,6 +304,11 @@ getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
throw "Could not find 'INSERT_SUBREG' instruction!";
const CodeGenInstruction *INSERT_SUBREG = &I->second;
I = getInstructions().find("IMPLICIT_DEF");
if (I == Instructions.end())
throw "Could not find 'IMPLICIT_DEF' instruction!";
const CodeGenInstruction *IMPLICIT_DEF = &I->second;
// Print out the rest of the instructions now.
NumberedInstructions.push_back(PHI);
NumberedInstructions.push_back(INLINEASM);
@ -311,13 +316,15 @@ getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
NumberedInstructions.push_back(DECLARE);
NumberedInstructions.push_back(EXTRACT_SUBREG);
NumberedInstructions.push_back(INSERT_SUBREG);
NumberedInstructions.push_back(IMPLICIT_DEF);
for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
if (&II->second != PHI &&
&II->second != INLINEASM &&
&II->second != LABEL &&
&II->second != DECLARE &&
&II->second != EXTRACT_SUBREG &&
&II->second != INSERT_SUBREG)
&II->second != INSERT_SUBREG &&
&II->second != IMPLICIT_DEF)
NumberedInstructions.push_back(&II->second);
}

8
utils/TableGen/DAGISelEmitter.cpp
View File

@ -1826,6 +1826,11 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
<< " return New.Val;\n"
<< "}\n\n";
OS << "SDNode *Select_UNDEF(const SDOperand &N) {\n"
<< " return CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,\n"
<< " N.getValueType());\n"
<< "}\n\n";
OS << "SDNode *Select_LABEL(const SDOperand &N) {\n"
<< " SDOperand Chain = N.getOperand(0);\n"
<< " SDOperand N1 = N.getOperand(1);\n"
@ -1926,7 +1931,8 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
<< " case ISD::LABEL: return Select_LABEL(N);\n"
<< " case ISD::DECLARE: return Select_DECLARE(N);\n"
<< " case ISD::EXTRACT_SUBREG: return Select_EXTRACT_SUBREG(N);\n"
<< " case ISD::INSERT_SUBREG: return Select_INSERT_SUBREG(N);\n";
<< " case ISD::INSERT_SUBREG: return Select_INSERT_SUBREG(N);\n"
<< " case ISD::UNDEF: return Select_UNDEF(N);\n";
// Loop over all of the case statements, emiting a call to each method we

3
utils/TableGen/InstrInfoEmitter.cpp
View File

@ -411,7 +411,8 @@ void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
R->getName() != "LABEL" &&
R->getName() != "DECLARE" &&
R->getName() != "EXTRACT_SUBREG" &&
R->getName() != "INSERT_SUBREG")
R->getName() != "INSERT_SUBREG" &&
R->getName() != "IMPLICIT_DEF")
throw R->getName() + " doesn't have a field named '" +
Val->getValue() + "'!";
return;