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https://github.com/c64scene-ar/llvm-6502.git
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This target does not support/want ISD::BRCONDTWOWAY
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21164 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -62,6 +62,7 @@ namespace {
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addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass);
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addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass);
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setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
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setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
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setOperationAction(ISD::EXTLOAD , MVT::f32 , Promote);
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@ -55,6 +55,7 @@ namespace {
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// register class for predicate registers
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addRegisterClass(MVT::i1, IA64::PRRegisterClass);
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setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
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setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
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setSetCCResultType(MVT::i1);
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@ -56,6 +56,7 @@ namespace {
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// well.
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/**/ addRegisterClass(MVT::i1, X86::R8RegisterClass);
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setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
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setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
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setOperationAction(ISD::ZERO_EXTEND_INREG, MVT::i16 , Expand);
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