mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD)
Note: There's a later patch on my branch that re-implements this to select
build_vector without the custom SelectionDAG nodes. The future patch avoids
the constant-folding problems stemming from the custom node (i.e. it doesn't
need to re-implement all the DAG combines related to BUILD_VECTOR).
Changes to MIPS specific SelectionDAG nodes:
* Added VSPLAT
This is a special case of BUILD_VECTOR that covers the case the
BUILD_VECTOR is a splat operation.
* Added VSPLATD
This is a special case of VSPLAT that handles the cases when v2i64 is legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
669b966861
commit
da521cc1cc
@ -212,6 +212,8 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
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case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
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case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
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case MipsISD::VSPLAT: return "MipsISD::VSPLAT";
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case MipsISD::VSPLATD: return "MipsISD::VSPLATD";
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default: return NULL;
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}
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}
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@ -152,12 +152,18 @@ namespace llvm {
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SETCC_DSP,
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SELECT_CC_DSP,
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// Vector comparisons
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// Vector comparisons.
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VALL_ZERO,
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VANY_ZERO,
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VALL_NONZERO,
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VANY_NONZERO,
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// Special case of BUILD_VECTOR where all elements are the same.
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VSPLAT,
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// Special case of VSPLAT where the result is v2i64, the operand is
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// constant, and the operand fits in a signed 10-bits value.
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VSPLATD,
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// Load/Store Left/Right nodes.
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LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LWR,
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@ -11,12 +11,20 @@
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//
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//===----------------------------------------------------------------------===//
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def SDT_MipsSplat : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisInt<1>]>;
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def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
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def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
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def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
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def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
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def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
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def MipsVSplat : SDNode<"MipsISD::VSPLAT", SDT_MipsSplat>;
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def MipsVSplatD : SDNode<"MipsISD::VSPLATD", SDT_MipsSplat>;
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def vsplati8 : PatFrag<(ops node:$in), (v16i8 (MipsVSplat (i32 node:$in)))>;
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def vsplati16 : PatFrag<(ops node:$in), (v8i16 (MipsVSplat (i32 node:$in)))>;
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def vsplati32 : PatFrag<(ops node:$in), (v4i32 (MipsVSplat (i32 node:$in)))>;
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def vsplati64 : PatFrag<(ops node:$in), (v2i64 (MipsVSplatD (i32 node:$in)))>;
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// Immediates
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def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>;
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@ -1383,12 +1391,9 @@ class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
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class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
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MSA128D, MSA128W>;
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class FILL_B_DESC : MSA_2R_DESC_BASE<"fill.b", int_mips_fill_b,
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MSA128B, GPR32>;
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class FILL_H_DESC : MSA_2R_DESC_BASE<"fill.h", int_mips_fill_h,
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MSA128H, GPR32>;
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class FILL_W_DESC : MSA_2R_DESC_BASE<"fill.w", int_mips_fill_w,
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MSA128W, GPR32>;
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class FILL_B_DESC : MSA_2R_DESC_BASE<"fill.b", vsplati8, MSA128B, GPR32>;
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class FILL_H_DESC : MSA_2R_DESC_BASE<"fill.h", vsplati16, MSA128H, GPR32>;
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class FILL_W_DESC : MSA_2R_DESC_BASE<"fill.w", vsplati32, MSA128W, GPR32>;
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class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128W>;
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class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128D>;
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@ -1573,10 +1578,10 @@ class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128H>;
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class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128W>;
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class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128D>;
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class LDI_B_DESC : MSA_I10_DESC_BASE<"ldi.b", int_mips_ldi_b, MSA128B>;
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class LDI_H_DESC : MSA_I10_DESC_BASE<"ldi.h", int_mips_ldi_h, MSA128H>;
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class LDI_W_DESC : MSA_I10_DESC_BASE<"ldi.w", int_mips_ldi_w, MSA128W>;
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class LDI_D_DESC : MSA_I10_DESC_BASE<"ldi.d", int_mips_ldi_d, MSA128D>;
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class LDI_B_DESC : MSA_I10_DESC_BASE<"ldi.b", vsplati8, MSA128B>;
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class LDI_H_DESC : MSA_I10_DESC_BASE<"ldi.h", vsplati16, MSA128H>;
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class LDI_W_DESC : MSA_I10_DESC_BASE<"ldi.w", vsplati32, MSA128W>;
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class LDI_D_DESC : MSA_I10_DESC_BASE<"ldi.d", vsplati64, MSA128D>;
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class LDX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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ValueType TyNode, RegisterClass RCWD,
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@ -2356,6 +2361,7 @@ def LD_D: LD_D_ENC, LD_D_DESC;
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def LDI_B : LDI_B_ENC, LDI_B_DESC;
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def LDI_H : LDI_H_ENC, LDI_H_DESC;
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def LDI_W : LDI_W_ENC, LDI_W_DESC;
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def LDI_D : LDI_D_ENC, LDI_D_DESC;
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def LDX_B: LDX_B_ENC, LDX_B_DESC;
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def LDX_H: LDX_H_ENC, LDX_H_DESC;
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@ -147,6 +147,7 @@ llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
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return new MipsSETargetLowering(TM);
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}
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// Enable MSA support for the given integer type and Register class.
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void MipsSETargetLowering::
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addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
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addRegisterClass(Ty, RC);
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@ -158,6 +159,7 @@ addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
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setOperationAction(ISD::BITCAST, Ty, Legal);
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setOperationAction(ISD::LOAD, Ty, Legal);
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setOperationAction(ISD::STORE, Ty, Legal);
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setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
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setOperationAction(ISD::ADD, Ty, Legal);
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setOperationAction(ISD::CTLZ, Ty, Legal);
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@ -170,6 +172,7 @@ addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
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setOperationAction(ISD::UDIV, Ty, Legal);
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}
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// Enable MSA support for the given floating-point type and Register class.
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void MipsSETargetLowering::
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addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
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addRegisterClass(Ty, RC);
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@ -224,6 +227,7 @@ SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
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case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
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case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
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case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
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}
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return MipsTargetLowering::LowerOperation(Op, DAG);
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@ -921,6 +925,10 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
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case Intrinsic::mips_fdiv_w:
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case Intrinsic::mips_fdiv_d:
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return lowerMSABinaryIntr(Op, DAG, ISD::FDIV);
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case Intrinsic::mips_fill_b:
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case Intrinsic::mips_fill_h:
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case Intrinsic::mips_fill_w:
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return lowerMSAUnaryIntr(Op, DAG, MipsISD::VSPLAT);
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case Intrinsic::mips_flog2_w:
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case Intrinsic::mips_flog2_d:
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return lowerMSAUnaryIntr(Op, DAG, ISD::FLOG2);
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@ -936,6 +944,11 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
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case Intrinsic::mips_fsub_w:
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case Intrinsic::mips_fsub_d:
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return lowerMSABinaryIntr(Op, DAG, ISD::FSUB);
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case Intrinsic::mips_ldi_b:
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case Intrinsic::mips_ldi_h:
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case Intrinsic::mips_ldi_w:
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case Intrinsic::mips_ldi_d:
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return lowerMSAUnaryIntr(Op, DAG, MipsISD::VSPLAT);
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case Intrinsic::mips_mulv_b:
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case Intrinsic::mips_mulv_h:
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case Intrinsic::mips_mulv_w:
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@ -1073,6 +1086,102 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
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}
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}
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/// \brief Check if the given BuildVectorSDNode is a splat.
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/// This method currently relies on DAG nodes being reused when equivalent,
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/// so it's possible for this to return false even when isConstantSplat returns
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/// true.
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static bool isSplatVector(const BuildVectorSDNode *N) {
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EVT VT = N->getValueType(0);
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assert(VT.isVector() && "Expected a vector type");
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unsigned int nOps = N->getNumOperands();
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assert(nOps > 1 && "isSplat has 0 or 1 sized build vector");
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SDValue Operand0 = N->getOperand(0);
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for (unsigned int i = 1; i < nOps; ++i) {
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if (N->getOperand(i) != Operand0)
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return false;
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}
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return true;
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}
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// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
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// backend.
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//
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// Lowers according to the following rules:
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// - Vectors of 128-bits may be legal subject to the other rules. Other sizes
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// are not legal.
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// - Non-constant splats are legal and are lowered to MipsISD::VSPLAT.
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// - Constant splats with an element size of 32-bits or less are legal and are
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// lowered to MipsISD::VSPLAT.
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// - Constant splats with an element size of 64-bits but whose value would fit
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// within a 10 bit immediate are legal and are lowered to MipsISD::VSPLATD.
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// - All other ISD::BUILD_VECTORS are not legal
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SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
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SelectionDAG &DAG) const {
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BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
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EVT ResTy = Op->getValueType(0);
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SDLoc DL(Op);
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APInt SplatValue, SplatUndef;
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unsigned SplatBitSize;
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bool HasAnyUndefs;
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if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
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return SDValue();
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if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
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HasAnyUndefs, 8,
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!Subtarget->isLittle())) {
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SDValue Result;
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EVT TmpVecTy;
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EVT ConstTy = MVT::i32;
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unsigned SplatOp = MipsISD::VSPLAT;
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switch (SplatBitSize) {
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default:
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return SDValue();
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case 64:
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TmpVecTy = MVT::v2i64;
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// i64 is an illegal type on Mips32, but if it the constant fits into a
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// signed 10-bit value then we can still handle it using VSPLATD and an
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// i32 constant
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if (HasMips64)
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ConstTy = MVT::i64;
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else if (isInt<10>(SplatValue.getSExtValue())) {
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SplatValue = SplatValue.trunc(32);
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SplatOp = MipsISD::VSPLATD;
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} else
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return SDValue();
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break;
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case 32:
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TmpVecTy = MVT::v4i32;
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break;
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case 16:
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TmpVecTy = MVT::v8i16;
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SplatValue = SplatValue.sext(32);
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break;
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case 8:
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TmpVecTy = MVT::v16i8;
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SplatValue = SplatValue.sext(32);
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break;
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}
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Result = DAG.getNode(SplatOp, DL, TmpVecTy,
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DAG.getConstant(SplatValue, ConstTy));
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if (ResTy != Result.getValueType())
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Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result);
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return Result;
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}
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else if (isSplatVector(Node))
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return DAG.getNode(MipsISD::VSPLAT, DL, ResTy, Op->getOperand(0));
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return SDValue();
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}
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MachineBasicBlock * MipsSETargetLowering::
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emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
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// $bb:
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@ -22,7 +22,11 @@ namespace llvm {
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public:
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explicit MipsSETargetLowering(MipsTargetMachine &TM);
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/// \brief Enable MSA support for the given integer type and Register
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/// class.
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void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
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/// \brief Enable MSA support for the given floating-point type and
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/// Register class.
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void addMSAFloatType(MVT::SimpleValueType Ty,
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const TargetRegisterClass *RC);
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@ -69,6 +73,7 @@ namespace llvm {
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SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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120
test/CodeGen/Mips/msa/basic_operations.ll
Normal file
120
test/CodeGen/Mips/msa/basic_operations.ll
Normal file
@ -0,0 +1,120 @@
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; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=MIPS32 %s
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@v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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@v8i16 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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@v4i32 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>
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@v2i64 = global <2 x i64> <i64 0, i64 0>
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@i64 = global i64 0
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define void @const_v16i8() nounwind {
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; MIPS32: const_v16i8:
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store volatile <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8>*@v16i8
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; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
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store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8>*@v16i8
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; MIPS32: ldi.b [[R1:\$w[0-9]+]], 1
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store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 31>, <16 x i8>*@v16i8
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; MIPS32: ld.b [[R1:\$w[0-9]+]], %lo(
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store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6>, <16 x i8>*@v16i8
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; MIPS32: ld.b [[R1:\$w[0-9]+]], %lo(
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store volatile <16 x i8> <i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 1, i8 2>, <16 x i8>*@v16i8
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; MIPS32: ldi.h [[R1:\$w[0-9]+]], 258
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store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>, <16 x i8>*@v16i8
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; MIPS32-DAG: lui [[R2:\$[0-9]+]], 258
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; MIPS32-DAG: ori [[R2]], [[R2]], 772
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; MIPS32-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
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store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>*@v16i8
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; MIPS32: ld.b [[R1:\$w[0-9]+]], %lo(
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ret void
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; MIPS32: .size const_v16i8
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}
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define void @const_v8i16() nounwind {
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; MIPS32: const_v8i16:
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store volatile <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16>*@v8i16
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; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
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store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16>*@v8i16
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; MIPS32: ldi.h [[R1:\$w[0-9]+]], 1
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store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 2, i16 1, i16 1, i16 1, i16 31>, <8 x i16>*@v8i16
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; MIPS32: ld.h [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
store volatile <8 x i16> <i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028>, <8 x i16>*@v8i16
|
||||
; MIPS32: ldi.b [[R1:\$w[0-9]+]], 4
|
||||
|
||||
store volatile <8 x i16> <i16 1, i16 2, i16 1, i16 2, i16 1, i16 2, i16 1, i16 2>, <8 x i16>*@v8i16
|
||||
; MIPS32-DAG: lui [[R2:\$[0-9]+]], 1
|
||||
; MIPS32-DAG: ori [[R2]], [[R2]], 2
|
||||
; MIPS32-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
|
||||
|
||||
store volatile <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>, <8 x i16>*@v8i16
|
||||
; MIPS32: ld.h [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
ret void
|
||||
; MIPS32: .size const_v8i16
|
||||
}
|
||||
|
||||
define void @const_v4i32() nounwind {
|
||||
; MIPS32: const_v4i32:
|
||||
|
||||
store volatile <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32>*@v4i32
|
||||
; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
|
||||
|
||||
store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32>*@v4i32
|
||||
; MIPS32: ldi.w [[R1:\$w[0-9]+]], 1
|
||||
|
||||
store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 31>, <4 x i32>*@v4i32
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
store volatile <4 x i32> <i32 16843009, i32 16843009, i32 16843009, i32 16843009>, <4 x i32>*@v4i32
|
||||
; MIPS32: ldi.b [[R1:\$w[0-9]+]], 1
|
||||
|
||||
store volatile <4 x i32> <i32 65537, i32 65537, i32 65537, i32 65537>, <4 x i32>*@v4i32
|
||||
; MIPS32: ldi.h [[R1:\$w[0-9]+]], 1
|
||||
|
||||
store volatile <4 x i32> <i32 1, i32 2, i32 1, i32 2>, <4 x i32>*@v4i32
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
store volatile <4 x i32> <i32 3, i32 4, i32 5, i32 6>, <4 x i32>*@v4i32
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
ret void
|
||||
; MIPS32: .size const_v4i32
|
||||
}
|
||||
|
||||
define void @const_v2i64() nounwind {
|
||||
; MIPS32: const_v2i64:
|
||||
|
||||
store volatile <2 x i64> <i64 0, i64 0>, <2 x i64>*@v2i64
|
||||
; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
|
||||
|
||||
store volatile <2 x i64> <i64 72340172838076673, i64 72340172838076673>, <2 x i64>*@v2i64
|
||||
; MIPS32: ldi.b [[R1:\$w[0-9]+]], 1
|
||||
|
||||
store volatile <2 x i64> <i64 281479271743489, i64 281479271743489>, <2 x i64>*@v2i64
|
||||
; MIPS32: ldi.h [[R1:\$w[0-9]+]], 1
|
||||
|
||||
store volatile <2 x i64> <i64 4294967297, i64 4294967297>, <2 x i64>*@v2i64
|
||||
; MIPS32: ldi.w [[R1:\$w[0-9]+]], 1
|
||||
|
||||
store volatile <2 x i64> <i64 1, i64 1>, <2 x i64>*@v2i64
|
||||
; MIPS32: ldi.d [[R1:\$w[0-9]+]], 1
|
||||
|
||||
store volatile <2 x i64> <i64 1, i64 31>, <2 x i64>*@v2i64
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
store volatile <2 x i64> <i64 3, i64 4>, <2 x i64>*@v2i64
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
ret void
|
||||
; MIPS32: .size const_v2i64
|
||||
}
|
||||
57
test/CodeGen/Mips/msa/basic_operations_float.ll
Normal file
57
test/CodeGen/Mips/msa/basic_operations_float.ll
Normal file
@ -0,0 +1,57 @@
|
||||
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=MIPS32 %s
|
||||
|
||||
@v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
|
||||
@v2f64 = global <2 x double> <double 0.0, double 0.0>
|
||||
|
||||
define void @const_v4f32() nounwind {
|
||||
; MIPS32: const_v4f32:
|
||||
|
||||
store volatile <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>*@v4f32
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float>*@v4f32
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
|
||||
; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
ret void
|
||||
; MIPS32: .size const_v4f32
|
||||
}
|
||||
|
||||
define void @const_v2f64() nounwind {
|
||||
; MIPS32: const_v2f64:
|
||||
|
||||
store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
|
||||
; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
|
||||
|
||||
ret void
|
||||
; MIPS32: .size const_v2f64
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user