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[X86][FastISel] Simplify the logic in method X86SelectSIToFP.

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The target-independent selection algorithm in FastISel already knows how
to select a SINT_TO_FP if the target is SSE but not AVX.

On targets that have SSE but not AVX, the tablegen'd 'fastEmit' functions
for ISD::SINT_TO_FP know how to select instruction X86::CVTSI2SSrr
(for an i32 to f32 conversion) and X86::CVTSI2SDrr (for an i32 to f64
conversion).

This patch simplifies the logic in method X86SelectSIToFP knowing that
the code would not be reachable if the subtarget doesn't have AVX.
No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231243 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
2015-03-04 14:23:25 +00:00
parent 826cbaf934
commit da5e5688e9
2 changed files with 15 additions and 23 deletions
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34
lib/Target/X86/X86FastISel.cpp
View File

@@ -2015,38 +2015,30 @@ bool X86FastISel::X86SelectSIToFP(const Instruction *I) {
if (OpReg == 0) if (OpReg == 0)
return false; return false;
bool HasAVX = Subtarget->hasAVX();
const TargetRegisterClass *RC = nullptr; const TargetRegisterClass *RC = nullptr;
unsigned Opcode; unsigned Opcode;
if (I->getType()->isDoubleTy() && X86ScalarSSEf64) { if (I->getType()->isDoubleTy()) {
// sitofp int -> double // sitofp int -> double
Opcode = HasAVX ? X86::VCVTSI2SDrr : X86::CVTSI2SDrr; Opcode = X86::VCVTSI2SDrr;
RC = &X86::FR64RegClass; RC = &X86::FR64RegClass;
} else if (I->getType()->isFloatTy() && X86ScalarSSEf32) { } else if (I->getType()->isFloatTy()) {
// sitofp int -> float // sitofp int -> float
Opcode = HasAVX ? X86::VCVTSI2SSrr : X86::CVTSI2SSrr; Opcode = X86::VCVTSI2SSrr;
RC = &X86::FR32RegClass; RC = &X86::FR32RegClass;
} else } else
return false; return false;
// The target-independent selection algorithm in FastISel already knows how
// to select a SINT_TO_FP if the target is SSE but not AVX. This code is only
// reachable if the subtarget has AVX.
assert(Subtarget->hasAVX() && "Expected a subtarget with AVX!");
unsigned ImplicitDefReg = 0; unsigned ImplicitDefReg = createResultReg(RC);
if (HasAVX) { BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
ImplicitDefReg = createResultReg(RC); TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, unsigned ResultReg =
TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg); fastEmitInst_rr(Opcode, RC, ImplicitDefReg, true, OpReg, false);
}
const MCInstrDesc &II = TII.get(Opcode);
OpReg = constrainOperandRegClass(II, OpReg, (HasAVX ? 2 : 1));
unsigned ResultReg = createResultReg(RC);
MachineInstrBuilder MIB;
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
if (ImplicitDefReg)
MIB.addReg(ImplicitDefReg, RegState::Kill);
MIB.addReg(OpReg);
updateValueMap(I, ResultReg); updateValueMap(I, ResultReg);
return true; return true;
} }

4
test/CodeGen/X86/fast-isel-int-float-conversion.ll
View File

@@ -1,5 +1,5 @@
; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+sse2 -O0 --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE2 ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+sse2 -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx -O0 --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX
define double @int_to_double_rr(i32 %a) { define double @int_to_double_rr(i32 %a) {