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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-12 17:32:19 +00:00
no need to expand ISD::TRAP to X86ISD::TRAP, just match ISD::TRAP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46015 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -294,7 +294,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
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setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
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setOperationAction(ISD::TRAP, MVT::Other, Custom);
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setOperationAction(ISD::TRAP, MVT::Other, Legal);
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// VASTART needs to be custom lowered to use the VarArgsFrameIndex
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// VASTART needs to be custom lowered to use the VarArgsFrameIndex
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setOperationAction(ISD::VASTART , MVT::Other, Custom);
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setOperationAction(ISD::VASTART , MVT::Other, Custom);
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@ -4950,10 +4950,6 @@ SDOperand X86TargetLowering::LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG) {
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ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
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ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
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}
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}
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SDOperand X86TargetLowering::LowerTRAP(SDOperand Op, SelectionDAG &DAG) {
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return DAG.getNode(X86ISD::TRAP, MVT::Other, Op.getOperand(0));
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}
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SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) {
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SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) {
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MVT::ValueType VT = Op.getValueType();
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MVT::ValueType VT = Op.getValueType();
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MVT::ValueType OpVT = VT;
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MVT::ValueType OpVT = VT;
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@ -5058,7 +5054,6 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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case ISD::FLT_ROUNDS: return LowerFLT_ROUNDS(Op, DAG);
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case ISD::FLT_ROUNDS: return LowerFLT_ROUNDS(Op, DAG);
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case ISD::CTLZ: return LowerCTLZ(Op, DAG);
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case ISD::CTLZ: return LowerCTLZ(Op, DAG);
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case ISD::CTTZ: return LowerCTTZ(Op, DAG);
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case ISD::CTTZ: return LowerCTTZ(Op, DAG);
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case ISD::TRAP: return LowerTRAP(Op, DAG);
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// FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
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// FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
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case ISD::READCYCLECOUNTER:
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case ISD::READCYCLECOUNTER:
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@ -5098,7 +5093,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::CALL: return "X86ISD::CALL";
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case X86ISD::CALL: return "X86ISD::CALL";
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case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
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case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
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case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
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case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
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case X86ISD::TRAP: return "X86ISD::TRAP";
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case X86ISD::CMP: return "X86ISD::CMP";
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case X86ISD::CMP: return "X86ISD::CMP";
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case X86ISD::COMI: return "X86ISD::COMI";
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case X86ISD::COMI: return "X86ISD::COMI";
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case X86ISD::UCOMI: return "X86ISD::UCOMI";
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case X86ISD::UCOMI: return "X86ISD::UCOMI";
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@ -197,10 +197,7 @@ namespace llvm {
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TC_RETURN,
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TC_RETURN,
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// Store FP control world into i16 memory
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// Store FP control world into i16 memory
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FNSTCW16m,
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FNSTCW16m
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// Trapping instruction
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TRAP
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};
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};
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}
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}
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@ -487,7 +484,6 @@ namespace llvm {
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SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerTRAP(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG);
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SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
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SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
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@ -57,8 +57,6 @@ def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
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def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
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def SDT_X86TRAP : SDTypeProfile<0, 0, []>;
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def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
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def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
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def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
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def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
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def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
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def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
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@ -109,8 +107,9 @@ def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
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def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
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def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
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[SDNPHasChain, SDNPOptInFlag]>;
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[SDNPHasChain, SDNPOptInFlag]>;
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def X86trap : SDNode<"X86ISD::TRAP", SDT_X86TRAP,
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def SDT_TRAP : SDTypeProfile<0, 0, []>;
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[SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
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def trap : SDNode<"ISD::TRAP", SDT_TRAP,
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[SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// X86 Operand Definitions.
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// X86 Operand Definitions.
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@ -490,7 +489,7 @@ def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
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TB;
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TB;
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let isBarrier = 1, hasCtrlDep = 1 in {
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let isBarrier = 1, hasCtrlDep = 1 in {
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def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(X86trap)]>, TB;
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def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
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}
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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