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Correct some BuildMI arguments for the upcoming simple scheduler

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16519 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2004-09-27 05:08:17 +00:00
parent c6e7430499
commit da721e74f8
3 changed files with 3 additions and 3 deletions
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2
lib/Target/PowerPC/PPC32ISelSimple.cpp
View File

@ -557,7 +557,7 @@ void PPC32ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
GlobalBaseReg = makeAnotherReg(Type::IntTy);
BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
BuildMI(FirstMBB, MBBI, PPC::MFLR, 0, GlobalBaseReg).addReg(PPC::LR);
BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR);
GlobalBaseInitialized = true;
}
// Emit our copy of GlobalBaseReg to the destination register in the

2
lib/Target/PowerPC/PPC64RegisterInfo.cpp
View File

@ -78,7 +78,7 @@ PPC64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
const TargetRegisterClass *RC = getRegClass(SrcReg);
unsigned OC = Opcode[getIdx(RC)];
if (SrcReg == PPC::LR) {
BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11);
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
} else {

2
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -78,7 +78,7 @@ PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
unsigned OC = Opcode[getIdx(RC)];
if (SrcReg == PPC::LR) {
BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11);
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
} else {