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Correct some BuildMI arguments for the upcoming simple scheduler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16519 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -557,7 +557,7 @@ void PPC32ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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GlobalBaseReg = makeAnotherReg(Type::IntTy);
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BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
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BuildMI(FirstMBB, MBBI, PPC::MFLR, 0, GlobalBaseReg).addReg(PPC::LR);
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BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR);
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GlobalBaseInitialized = true;
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}
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// Emit our copy of GlobalBaseReg to the destination register in the
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@ -78,7 +78,7 @@ PPC64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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const TargetRegisterClass *RC = getRegClass(SrcReg);
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unsigned OC = Opcode[getIdx(RC)];
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if (SrcReg == PPC::LR) {
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BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11);
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BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
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BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
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addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
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} else {
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@ -78,7 +78,7 @@ PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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unsigned OC = Opcode[getIdx(RC)];
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if (SrcReg == PPC::LR) {
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BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11);
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BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
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BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
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addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
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} else {
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