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Improve pattern match from v1i8 to v1i32 for AArch64 Neon.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200119 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jiangning Liu 2014-01-26 04:55:53 +00:00
parent e1631e8729
commit da77e83632
2 changed files with 23 additions and 14 deletions
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34
lib/Target/AArch64/AArch64InstrNEON.td
View File

@ -6233,23 +6233,21 @@ multiclass NeonI_ext<string prefix, SDNode ExtOp> {
(v8i16 (!cast<Instruction>(prefix # "_8B")
(v8i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), 0)),
sub_16)>;
// v1i8 -> v1i32
def : Pat<(v1i32 (ExtOp (v1i8 FPR8:$Rn))),
(EXTRACT_SUBREG
(v4i32 (!cast<Instruction>(prefix # "_4H")
(v4i16 (SUBREG_TO_REG (i64 0),
(v1i16 (EXTRACT_SUBREG
(v8i16 (!cast<Instruction>(prefix # "_8B")
(v8i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), 0)),
sub_16)),
sub_16)), 0)),
sub_32)>;
}
defm NeonI_zext : NeonI_ext<"USHLLvvi", zext>;
defm NeonI_sext : NeonI_ext<"SSHLLvvi", sext>;
// zext v1i8 -> v1i32
def : Pat<(v1i32 (zext (v1i8 FPR8:$Rn))),
(v1i32 (EXTRACT_SUBREG
(v1i64 (SUBREG_TO_REG (i64 0),
(v1i8 (DUPbv_B
(v16i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)),
0)),
sub_8)),
sub_32))>;
// zext v1i8 -> v1i64
def : Pat<(v1i64 (zext (v1i8 FPR8:$Rn))),
(v1i64 (SUBREG_TO_REG (i64 0),
@ -6266,6 +6264,18 @@ def : Pat<(v1i64 (zext (v1i16 FPR16:$Rn))),
0)),
sub_16))>;
// sext v1i8 -> v1i32
def : Pat<(v1i32 (sext (v1i8 FPR8:$Rn))),
(EXTRACT_SUBREG
(v4i32 (SSHLLvvi_4H
(v4i16 (SUBREG_TO_REG (i64 0),
(v1i16 (EXTRACT_SUBREG
(v8i16 (SSHLLvvi_8B
(v8i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), 0)),
sub_16)),
sub_16)), 0)),
sub_32)>;
// sext v1i8 -> v1i64
def : Pat<(v1i64 (sext (v1i8 FPR8:$Rn))),
(EXTRACT_SUBREG

3
test/CodeGen/AArch64/neon-scalar-ext.ll
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@ -29,8 +29,7 @@ define <1 x i16> @test_zext_v1i8_v1i16(<8 x i8> %v) nounwind readnone {
define <1 x i32> @test_zext_v1i8_v1i32(<8 x i8> %v) nounwind readnone {
; CHECK-LABEL: test_zext_v1i8_v1i32:
; CHECK: ushll v0.8h, v0.8b, #0
; CHECK: ushll v0.4s, v0.4h, #0
; CHECK: dup b0, v0.b[0]
%1 = extractelement <8 x i8> %v, i32 0
%2 = insertelement <1 x i8> undef, i8 %1, i32 0
%3 = zext <1 x i8> %2 to <1 x i32>