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Improve pattern match from v1i8 to v1i32 for AArch64 Neon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200119 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -6233,23 +6233,21 @@ multiclass NeonI_ext<string prefix, SDNode ExtOp> {
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(v8i16 (!cast<Instruction>(prefix # "_8B")
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(v8i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), 0)),
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sub_16)>;
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// v1i8 -> v1i32
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def : Pat<(v1i32 (ExtOp (v1i8 FPR8:$Rn))),
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(EXTRACT_SUBREG
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(v4i32 (!cast<Instruction>(prefix # "_4H")
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(v4i16 (SUBREG_TO_REG (i64 0),
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(v1i16 (EXTRACT_SUBREG
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(v8i16 (!cast<Instruction>(prefix # "_8B")
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(v8i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), 0)),
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sub_16)),
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sub_16)), 0)),
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sub_32)>;
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}
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defm NeonI_zext : NeonI_ext<"USHLLvvi", zext>;
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defm NeonI_sext : NeonI_ext<"SSHLLvvi", sext>;
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// zext v1i8 -> v1i32
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def : Pat<(v1i32 (zext (v1i8 FPR8:$Rn))),
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(v1i32 (EXTRACT_SUBREG
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(v1i64 (SUBREG_TO_REG (i64 0),
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(v1i8 (DUPbv_B
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(v16i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)),
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0)),
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sub_8)),
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sub_32))>;
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// zext v1i8 -> v1i64
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def : Pat<(v1i64 (zext (v1i8 FPR8:$Rn))),
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(v1i64 (SUBREG_TO_REG (i64 0),
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@ -6266,6 +6264,18 @@ def : Pat<(v1i64 (zext (v1i16 FPR16:$Rn))),
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0)),
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sub_16))>;
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// sext v1i8 -> v1i32
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def : Pat<(v1i32 (sext (v1i8 FPR8:$Rn))),
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(EXTRACT_SUBREG
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(v4i32 (SSHLLvvi_4H
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(v4i16 (SUBREG_TO_REG (i64 0),
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(v1i16 (EXTRACT_SUBREG
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(v8i16 (SSHLLvvi_8B
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(v8i8 (SUBREG_TO_REG (i64 0), $Rn, sub_8)), 0)),
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sub_16)),
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sub_16)), 0)),
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sub_32)>;
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// sext v1i8 -> v1i64
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def : Pat<(v1i64 (sext (v1i8 FPR8:$Rn))),
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(EXTRACT_SUBREG
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@ -29,8 +29,7 @@ define <1 x i16> @test_zext_v1i8_v1i16(<8 x i8> %v) nounwind readnone {
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define <1 x i32> @test_zext_v1i8_v1i32(<8 x i8> %v) nounwind readnone {
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; CHECK-LABEL: test_zext_v1i8_v1i32:
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; CHECK: ushll v0.8h, v0.8b, #0
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; CHECK: ushll v0.4s, v0.4h, #0
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; CHECK: dup b0, v0.b[0]
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%1 = extractelement <8 x i8> %v, i32 0
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%2 = insertelement <1 x i8> undef, i8 %1, i32 0
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%3 = zext <1 x i8> %2 to <1 x i32>
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