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Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.

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rdar://10529348


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-12-05 21:06:26 +00:00
parent 2bf08ec854
commit da84786bee
2 changed files with 22 additions and 0 deletions
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18
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -5200,6 +5200,24 @@ processInstruction(MCInst &Inst,
Inst = TmpInst;
}
break;
case ARM::t2ADDri12:
// If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
// mnemonic was used (not "addw"), encoding T3 is preferred.
if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
break;
Inst.setOpcode(ARM::t2ADDri);
Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
break;
case ARM::t2SUBri12:
// If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
// mnemonic was used (not "subw"), encoding T3 is preferred.
if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
break;
Inst.setOpcode(ARM::t2SUBri);
Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
break;
case ARM::tADDi8:
// If the immediate is in the range 0-7, we want tADDi3 iff Rd was
// explicitly specified. From the ARM ARM: "Encoding T1 is preferred

4
test/MC/ARM/basic-thumb2-instructions.s
View File

@ -74,6 +74,7 @@ _func:
addw r12, r6, #0x100
adds r1, r2, #0x1f0
add r2, #1
add r0, r0, #32
@ CHECK: itet eq @ encoding: [0x0a,0xbf]
@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d]
@ -87,6 +88,7 @@ _func:
@ CHECK: addw r12, r6, #256 @ encoding: [0x06,0xf2,0x00,0x1c]
@ CHECK: adds.w r1, r2, #496 @ encoding: [0x12,0xf5,0xf8,0x71]
@ CHECK: add.w r2, r2, #1 @ encoding: [0x02,0xf1,0x01,0x02]
@ CHECK: add.w r0, r0, #32 @ encoding: [0x00,0xf1,0x20,0x00]
@------------------------------------------------------------------------------
@ -2566,6 +2568,7 @@ _func:
subw r12, r6, #0x100
subs r1, r2, #0x1f0
sub r2, #1
sub r0, r0, #32
@ CHECK: itet eq @ encoding: [0x0a,0xbf]
@ CHECK: subeq r1, r2, #4 @ encoding: [0x11,0x1f]
@ -2579,6 +2582,7 @@ _func:
@ CHECK: subw r12, r6, #256 @ encoding: [0xa6,0xf2,0x00,0x1c]
@ CHECK: subs.w r1, r2, #496 @ encoding: [0xb2,0xf5,0xf8,0x71]
@ CHECK: sub.w r2, r2, #1 @ encoding: [0xa2,0xf1,0x01,0x02]
@ CHECK: sub.w r0, r0, #32 @ encoding: [0xa0,0xf1,0x20,0x00]
@------------------------------------------------------------------------------