Avoid creating two TargetLowering objects for each target.

Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57016 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-10-03 16:55:19 +00:00
parent 38217fef57
commit da8ac5fd91
11 changed files with 22 additions and 33 deletions

View File

@ -39,15 +39,13 @@ namespace {
class ARMDAGToDAGISel : public SelectionDAGISel {
ARMTargetMachine &TM;
ARMTargetLowering ARMLowering;
/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
/// make the right decision when generating code for different targets.
const ARMSubtarget *Subtarget;
public:
explicit ARMDAGToDAGISel(ARMTargetMachine &tm)
: SelectionDAGISel(ARMLowering), TM(tm), ARMLowering(tm),
: SelectionDAGISel(*tm.getTargetLowering()), TM(tm),
Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
}

View File

@ -40,8 +40,6 @@ namespace {
/// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
/// instructions for SelectionDAG operations.
class AlphaDAGToDAGISel : public SelectionDAGISel {
AlphaTargetLowering AlphaLowering;
static const int64_t IMM_LOW = -32768;
static const int64_t IMM_HIGH = 32767;
static const int64_t IMM_MULT = 65536;
@ -147,8 +145,7 @@ namespace {
public:
explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
: SelectionDAGISel(AlphaLowering),
AlphaLowering(*TM.getTargetLowering())
: SelectionDAGISel(*TM.getTargetLowering())
{}
/// getI64Imm - Return a target constant with the specified value, of type

View File

@ -37,11 +37,10 @@ namespace {
/// instructions for SelectionDAG operations.
///
class IA64DAGToDAGISel : public SelectionDAGISel {
IA64TargetLowering IA64Lowering;
unsigned GlobalBaseReg;
public:
explicit IA64DAGToDAGISel(IA64TargetMachine &TM)
: SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
: SelectionDAGISel(*TM.getTargetLowering()) {}
virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary

View File

@ -52,19 +52,14 @@ class VISIBILITY_HIDDEN MipsDAGToDAGISel : public SelectionDAGISel {
/// TM - Keep a reference to MipsTargetMachine.
MipsTargetMachine &TM;
/// MipsLowering - This object fully describes how to lower LLVM code to an
/// Mips-specific SelectionDAG.
MipsTargetLowering MipsLowering;
/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
/// make the right decision when generating code for different targets.
const MipsSubtarget &Subtarget;
public:
explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
SelectionDAGISel(MipsLowering),
TM(tm), MipsLowering(*TM.getTargetLowering()),
Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
SelectionDAGISel(*tm.getTargetLowering()),
TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
virtual void InstructionSelect();

View File

@ -51,14 +51,10 @@ class VISIBILITY_HIDDEN PIC16DAGToDAGISel : public SelectionDAGISel {
/// TM - Keep a reference to PIC16TargetMachine.
PIC16TargetMachine &TM;
/// PIC16Lowering - This object fully describes how to lower LLVM code to an
/// PIC16-specific SelectionDAG.
PIC16TargetLowering PIC16Lowering;
public:
explicit PIC16DAGToDAGISel(PIC16TargetMachine &tm) :
SelectionDAGISel(PIC16Lowering),
TM(tm), PIC16Lowering(*TM.getTargetLowering()) {}
SelectionDAGISel(*tm.getTargetLowering()),
TM(tm) {}
virtual void InstructionSelect();

View File

@ -41,12 +41,12 @@ namespace {
///
class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel {
PPCTargetMachine &TM;
PPCTargetLowering PPCLowering;
PPCTargetLowering &PPCLowering;
const PPCSubtarget &PPCSubTarget;
unsigned GlobalBaseReg;
public:
explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
: SelectionDAGISel(PPCLowering), TM(tm),
: SelectionDAGISel(*tm.getTargetLowering()), TM(tm),
PPCLowering(*TM.getTargetLowering()),
PPCSubTarget(*TM.getSubtargetImpl()) {}

View File

@ -21,9 +21,10 @@
namespace llvm {
class FunctionPass;
class TargetMachine;
class SparcTargetMachine;
class raw_ostream;
FunctionPass *createSparcISelDag(TargetMachine &TM);
FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
FunctionPass *createSparcCodePrinterPass(raw_ostream &OS, TargetMachine &TM);
FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
FunctionPass *createSparcFPMoverPass(TargetMachine &TM);

View File

@ -29,14 +29,12 @@ using namespace llvm;
///
namespace {
class SparcDAGToDAGISel : public SelectionDAGISel {
SparcTargetLowering Lowering;
/// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
/// make the right decision when generating code for different targets.
const SparcSubtarget &Subtarget;
public:
explicit SparcDAGToDAGISel(TargetMachine &TM)
: SelectionDAGISel(Lowering), Lowering(TM),
explicit SparcDAGToDAGISel(SparcTargetMachine &TM)
: SelectionDAGISel(*TM.getTargetLowering()),
Subtarget(TM.getSubtarget<SparcSubtarget>()) {
}
@ -189,6 +187,6 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
/// createSparcISelDag - This pass converts a legalized DAG into a
/// SPARC-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
return new SparcDAGToDAGISel(TM);
}

View File

@ -30,7 +30,7 @@ const TargetAsmInfo *SparcTargetMachine::createTargetAsmInfo() const {
///
SparcTargetMachine::SparcTargetMachine(const Module &M, const std::string &FS)
: DataLayout("E-p:32:32-f128:128:128"),
Subtarget(M, FS), InstrInfo(Subtarget),
Subtarget(M, FS), TLInfo(*this), InstrInfo(Subtarget),
FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
}

View File

@ -19,6 +19,7 @@
#include "llvm/Target/TargetFrameInfo.h"
#include "SparcInstrInfo.h"
#include "SparcSubtarget.h"
#include "SparcISelLowering.h"
namespace llvm {
@ -27,6 +28,7 @@ class Module;
class SparcTargetMachine : public LLVMTargetMachine {
const TargetData DataLayout; // Calculates type size & alignment
SparcSubtarget Subtarget;
SparcTargetLowering TLInfo;
SparcInstrInfo InstrInfo;
TargetFrameInfo FrameInfo;
@ -42,6 +44,9 @@ public:
virtual const SparcRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
virtual SparcTargetLowering* getTargetLowering() const {
return const_cast<SparcTargetLowering*>(&TLInfo);
}
virtual const TargetData *getTargetData() const { return &DataLayout; }
static unsigned getModuleMatchQuality(const Module &M);

View File

@ -113,7 +113,7 @@ namespace {
/// X86Lowering - This object fully describes how to lower LLVM code to an
/// X86-specific SelectionDAG.
X86TargetLowering X86Lowering;
X86TargetLowering &X86Lowering;
/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
/// make the right decision when generating code for different targets.
@ -129,7 +129,7 @@ namespace {
public:
X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
: SelectionDAGISel(X86Lowering, fast),
: SelectionDAGISel(*tm.getTargetLowering(), fast),
TM(tm), X86Lowering(*TM.getTargetLowering()),
Subtarget(&TM.getSubtarget<X86Subtarget>()),
OptForSize(false) {}