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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128701 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -31,24 +31,24 @@ void SubtargetEmitter::Enumeration(raw_ostream &OS,
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// Open enumeration
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// Open enumeration
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OS << "enum {\n";
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OS << "enum {\n";
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// For each record
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// For each record
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for (unsigned i = 0, N = DefList.size(); i < N;) {
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for (unsigned i = 0, N = DefList.size(); i < N;) {
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// Next record
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// Next record
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Record *Def = DefList[i];
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Record *Def = DefList[i];
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// Get and emit name
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// Get and emit name
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OS << " " << Def->getName();
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OS << " " << Def->getName();
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// If bit flags then emit expression (1 << i)
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// If bit flags then emit expression (1 << i)
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if (isBits) OS << " = " << " 1 << " << i;
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if (isBits) OS << " = " << " 1 << " << i;
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// Depending on 'if more in the list' emit comma
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// Depending on 'if more in the list' emit comma
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if (++i < N) OS << ",";
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if (++i < N) OS << ",";
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OS << "\n";
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OS << "\n";
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}
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}
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// Close enumeration
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// Close enumeration
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OS << "};\n";
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OS << "};\n";
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}
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}
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@ -66,7 +66,7 @@ void SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
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// Begin feature table
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// Begin feature table
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OS << "// Sorted (by key) array of values for CPU features.\n"
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OS << "// Sorted (by key) array of values for CPU features.\n"
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<< "static const llvm::SubtargetFeatureKV FeatureKV[] = {\n";
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<< "static const llvm::SubtargetFeatureKV FeatureKV[] = {\n";
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// For each feature
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// For each feature
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for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) {
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for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) {
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// Next feature
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// Next feature
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@ -75,18 +75,18 @@ void SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
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const std::string &Name = Feature->getName();
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const std::string &Name = Feature->getName();
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const std::string &CommandLineName = Feature->getValueAsString("Name");
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const std::string &CommandLineName = Feature->getValueAsString("Name");
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const std::string &Desc = Feature->getValueAsString("Desc");
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const std::string &Desc = Feature->getValueAsString("Desc");
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if (CommandLineName.empty()) continue;
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if (CommandLineName.empty()) continue;
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// Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in }
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// Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in }
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OS << " { "
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OS << " { "
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<< "\"" << CommandLineName << "\", "
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<< "\"" << CommandLineName << "\", "
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<< "\"" << Desc << "\", "
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<< "\"" << Desc << "\", "
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<< Name << ", ";
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<< Name << ", ";
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const std::vector<Record*> &ImpliesList =
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const std::vector<Record*> &ImpliesList =
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Feature->getValueAsListOfDefs("Implies");
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Feature->getValueAsListOfDefs("Implies");
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if (ImpliesList.empty()) {
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if (ImpliesList.empty()) {
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OS << "0";
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OS << "0";
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} else {
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} else {
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@ -97,13 +97,13 @@ void SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
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}
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}
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OS << " }";
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OS << " }";
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// Depending on 'if more in the list' emit comma
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// Depending on 'if more in the list' emit comma
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if ((i + 1) < N) OS << ",";
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if ((i + 1) < N) OS << ",";
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OS << "\n";
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OS << "\n";
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}
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}
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// End feature table
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// End feature table
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OS << "};\n";
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OS << "};\n";
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@ -126,21 +126,21 @@ void SubtargetEmitter::CPUKeyValues(raw_ostream &OS) {
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// Begin processor table
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// Begin processor table
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OS << "// Sorted (by key) array of values for CPU subtype.\n"
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OS << "// Sorted (by key) array of values for CPU subtype.\n"
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<< "static const llvm::SubtargetFeatureKV SubTypeKV[] = {\n";
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<< "static const llvm::SubtargetFeatureKV SubTypeKV[] = {\n";
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// For each processor
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// For each processor
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for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
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for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
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// Next processor
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// Next processor
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Record *Processor = ProcessorList[i];
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Record *Processor = ProcessorList[i];
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const std::string &Name = Processor->getValueAsString("Name");
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const std::string &Name = Processor->getValueAsString("Name");
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const std::vector<Record*> &FeatureList =
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const std::vector<Record*> &FeatureList =
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Processor->getValueAsListOfDefs("Features");
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Processor->getValueAsListOfDefs("Features");
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// Emit as { "cpu", "description", f1 | f2 | ... fn },
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// Emit as { "cpu", "description", f1 | f2 | ... fn },
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OS << " { "
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OS << " { "
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<< "\"" << Name << "\", "
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<< "\"" << Name << "\", "
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<< "\"Select the " << Name << " processor\", ";
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<< "\"Select the " << Name << " processor\", ";
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if (FeatureList.empty()) {
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if (FeatureList.empty()) {
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OS << "0";
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OS << "0";
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} else {
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} else {
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@ -149,16 +149,16 @@ void SubtargetEmitter::CPUKeyValues(raw_ostream &OS) {
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if (++j < M) OS << " | ";
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if (++j < M) OS << " | ";
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}
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}
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}
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}
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// The "0" is for the "implies" section of this data structure.
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// The "0" is for the "implies" section of this data structure.
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OS << ", 0 }";
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OS << ", 0 }";
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// Depending on 'if more in the list' emit comma
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// Depending on 'if more in the list' emit comma
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if (++i < N) OS << ",";
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if (++i < N) OS << ",";
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OS << "\n";
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OS << "\n";
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}
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}
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// End processor table
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// End processor table
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OS << "};\n";
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OS << "};\n";
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@ -185,7 +185,7 @@ CollectAllItinClasses(raw_ostream &OS,
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// Assign itinerary class a unique number
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// Assign itinerary class a unique number
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ItinClassesMap[ItinClass->getName()] = i;
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ItinClassesMap[ItinClass->getName()] = i;
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}
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}
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// Emit size of table
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// Emit size of table
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OS<<"\nenum {\n";
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OS<<"\nenum {\n";
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OS<<" ItinClassesSize = " << N << "\n";
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OS<<" ItinClassesSize = " << N << "\n";
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@ -213,21 +213,21 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
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for (unsigned i = 0; i < N;) {
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for (unsigned i = 0; i < N;) {
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// Next stage
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// Next stage
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const Record *Stage = StageList[i];
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const Record *Stage = StageList[i];
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// Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
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// Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
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int Cycles = Stage->getValueAsInt("Cycles");
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int Cycles = Stage->getValueAsInt("Cycles");
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ItinString += " { " + itostr(Cycles) + ", ";
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ItinString += " { " + itostr(Cycles) + ", ";
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// Get unit list
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// Get unit list
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const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units");
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const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units");
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// For each unit
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// For each unit
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for (unsigned j = 0, M = UnitList.size(); j < M;) {
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for (unsigned j = 0, M = UnitList.size(); j < M;) {
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// Add name and bitwise or
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// Add name and bitwise or
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ItinString += Name + "FU::" + UnitList[j]->getName();
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ItinString += Name + "FU::" + UnitList[j]->getName();
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if (++j < M) ItinString += " | ";
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if (++j < M) ItinString += " | ";
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}
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}
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int TimeInc = Stage->getValueAsInt("TimeInc");
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int TimeInc = Stage->getValueAsInt("TimeInc");
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ItinString += ", " + itostr(TimeInc);
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ItinString += ", " + itostr(TimeInc);
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@ -256,7 +256,7 @@ void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData,
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for (unsigned i = 0; i < N;) {
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for (unsigned i = 0; i < N;) {
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// Next operand cycle
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// Next operand cycle
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const int OCycle = OperandCycleList[i];
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const int OCycle = OperandCycleList[i];
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ItinString += " " + itostr(OCycle);
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ItinString += " " + itostr(OCycle);
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if (++i < N) ItinString += ", ";
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if (++i < N) ItinString += ", ";
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}
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}
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@ -292,7 +292,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS,
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// Gather processor iteraries
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// Gather processor iteraries
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std::vector<Record*> ProcItinList =
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std::vector<Record*> ProcItinList =
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Records.getAllDerivedDefinitions("ProcessorItineraries");
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Records.getAllDerivedDefinitions("ProcessorItineraries");
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// If just no itinerary then don't bother
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// If just no itinerary then don't bother
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if (ProcItinList.size() < 2) return;
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if (ProcItinList.size() < 2) return;
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@ -332,7 +332,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS,
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// Begin stages table
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// Begin stages table
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std::string StageTable = "\nstatic const llvm::InstrStage Stages[] = {\n";
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std::string StageTable = "\nstatic const llvm::InstrStage Stages[] = {\n";
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StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
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StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
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// Begin operand cycle table
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// Begin operand cycle table
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std::string OperandCycleTable = "static const unsigned OperandCycles[] = {\n";
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std::string OperandCycleTable = "static const unsigned OperandCycles[] = {\n";
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OperandCycleTable += " 0, // No itinerary\n";
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OperandCycleTable += " 0, // No itinerary\n";
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@ -340,32 +340,32 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS,
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// Begin pipeline bypass table
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// Begin pipeline bypass table
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std::string BypassTable = "static const unsigned ForwardingPathes[] = {\n";
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std::string BypassTable = "static const unsigned ForwardingPathes[] = {\n";
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BypassTable += " 0, // No itinerary\n";
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BypassTable += " 0, // No itinerary\n";
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unsigned StageCount = 1, OperandCycleCount = 1;
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unsigned StageCount = 1, OperandCycleCount = 1;
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unsigned ItinStageEnum = 1, ItinOperandCycleEnum = 1;
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unsigned ItinStageEnum = 1, ItinOperandCycleEnum = 1;
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std::map<std::string, unsigned> ItinStageMap, ItinOperandMap;
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std::map<std::string, unsigned> ItinStageMap, ItinOperandMap;
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for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
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for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
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// Next record
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// Next record
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Record *Proc = ProcItinList[i];
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Record *Proc = ProcItinList[i];
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// Get processor itinerary name
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// Get processor itinerary name
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const std::string &Name = Proc->getName();
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const std::string &Name = Proc->getName();
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// Skip default
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// Skip default
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if (Name == "NoItineraries") continue;
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if (Name == "NoItineraries") continue;
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// Create and expand processor itinerary to cover all itinerary classes
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// Create and expand processor itinerary to cover all itinerary classes
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std::vector<InstrItinerary> ItinList;
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std::vector<InstrItinerary> ItinList;
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ItinList.resize(NItinClasses);
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ItinList.resize(NItinClasses);
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// Get itinerary data list
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// Get itinerary data list
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std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
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std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
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// For each itinerary data
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// For each itinerary data
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for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
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for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
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// Next itinerary data
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// Next itinerary data
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Record *ItinData = ItinDataList[j];
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Record *ItinData = ItinDataList[j];
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// Get string and stage count
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// Get string and stage count
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std::string ItinStageString;
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std::string ItinStageString;
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unsigned NStages;
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unsigned NStages;
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@ -394,7 +394,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS,
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ItinStageEnum++;
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ItinStageEnum++;
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}
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}
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}
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}
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// Check to see if operand cycle already exists and create if it doesn't
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// Check to see if operand cycle already exists and create if it doesn't
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unsigned FindOperandCycle = 0;
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unsigned FindOperandCycle = 0;
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if (NOperandCycles > 0) {
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if (NOperandCycles > 0) {
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@ -402,25 +402,25 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS,
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FindOperandCycle = ItinOperandMap[ItinOperandString];
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FindOperandCycle = ItinOperandMap[ItinOperandString];
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if (FindOperandCycle == 0) {
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if (FindOperandCycle == 0) {
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// Emit as cycle, // index
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// Emit as cycle, // index
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OperandCycleTable += ItinOperandCycleString + ", // " +
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OperandCycleTable += ItinOperandCycleString + ", // " +
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itostr(ItinOperandCycleEnum) + "\n";
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itostr(ItinOperandCycleEnum) + "\n";
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// Record Itin class number.
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// Record Itin class number.
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ItinOperandMap[ItinOperandCycleString] =
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ItinOperandMap[ItinOperandCycleString] =
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FindOperandCycle = OperandCycleCount;
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FindOperandCycle = OperandCycleCount;
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// Emit as bypass, // index
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// Emit as bypass, // index
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BypassTable += ItinBypassString + ", // " +
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BypassTable += ItinBypassString + ", // " +
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itostr(ItinOperandCycleEnum) + "\n";
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itostr(ItinOperandCycleEnum) + "\n";
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OperandCycleCount += NOperandCycles;
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OperandCycleCount += NOperandCycles;
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ItinOperandCycleEnum++;
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ItinOperandCycleEnum++;
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}
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}
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}
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}
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// Locate where to inject into processor itinerary table
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// Locate where to inject into processor itinerary table
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const std::string &Name = ItinData->getValueAsDef("TheClass")->getName();
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const std::string &Name = ItinData->getValueAsDef("TheClass")->getName();
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unsigned Find = ItinClassesMap[Name];
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unsigned Find = ItinClassesMap[Name];
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// Set up itinerary as location and location + stage count
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// Set up itinerary as location and location + stage count
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unsigned NumUOps = ItinClassList[Find]->getValueAsInt("NumMicroOps");
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unsigned NumUOps = ItinClassList[Find]->getValueAsInt("NumMicroOps");
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InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages,
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InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages,
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@ -430,7 +430,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS,
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// Inject - empty slots will be 0, 0
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// Inject - empty slots will be 0, 0
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ItinList[Find] = Intinerary;
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ItinList[Find] = Intinerary;
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}
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}
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// Add process itinerary to list
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// Add process itinerary to list
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ProcList.push_back(ItinList);
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ProcList.push_back(ItinList);
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}
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}
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@ -450,7 +450,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS,
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OS << StageTable;
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OS << StageTable;
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OS << OperandCycleTable;
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OS << OperandCycleTable;
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OS << BypassTable;
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OS << BypassTable;
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// Emit size of tables
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// Emit size of tables
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OS<<"\nenum {\n";
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OS<<"\nenum {\n";
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OS<<" StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage),\n";
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OS<<" StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage),\n";
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@ -466,7 +466,7 @@ void SubtargetEmitter::EmitProcessorData(raw_ostream &OS,
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// Get an iterator for processor itinerary stages
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// Get an iterator for processor itinerary stages
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std::vector<std::vector<InstrItinerary> >::iterator
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std::vector<std::vector<InstrItinerary> >::iterator
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ProcListIter = ProcList.begin();
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ProcListIter = ProcList.begin();
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// For each processor itinerary
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// For each processor itinerary
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std::vector<Record*> Itins =
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std::vector<Record*> Itins =
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Records.getAllDerivedDefinitions("ProcessorItineraries");
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Records.getAllDerivedDefinitions("ProcessorItineraries");
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@ -476,35 +476,35 @@ void SubtargetEmitter::EmitProcessorData(raw_ostream &OS,
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// Get processor itinerary name
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// Get processor itinerary name
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const std::string &Name = Itin->getName();
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const std::string &Name = Itin->getName();
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// Skip default
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// Skip default
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if (Name == "NoItineraries") continue;
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if (Name == "NoItineraries") continue;
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// Begin processor itinerary table
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// Begin processor itinerary table
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OS << "\n";
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OS << "\n";
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OS << "static const llvm::InstrItinerary " << Name << "[] = {\n";
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OS << "static const llvm::InstrItinerary " << Name << "[] = {\n";
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// For each itinerary class
|
// For each itinerary class
|
||||||
std::vector<InstrItinerary> &ItinList = *ProcListIter++;
|
std::vector<InstrItinerary> &ItinList = *ProcListIter++;
|
||||||
for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
|
for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
|
||||||
InstrItinerary &Intinerary = ItinList[j];
|
InstrItinerary &Intinerary = ItinList[j];
|
||||||
|
|
||||||
// Emit in the form of
|
// Emit in the form of
|
||||||
// { firstStage, lastStage, firstCycle, lastCycle } // index
|
// { firstStage, lastStage, firstCycle, lastCycle } // index
|
||||||
if (Intinerary.FirstStage == 0) {
|
if (Intinerary.FirstStage == 0) {
|
||||||
OS << " { 1, 0, 0, 0, 0 }";
|
OS << " { 1, 0, 0, 0, 0 }";
|
||||||
} else {
|
} else {
|
||||||
OS << " { " <<
|
OS << " { " <<
|
||||||
Intinerary.NumMicroOps << ", " <<
|
Intinerary.NumMicroOps << ", " <<
|
||||||
Intinerary.FirstStage << ", " <<
|
Intinerary.FirstStage << ", " <<
|
||||||
Intinerary.LastStage << ", " <<
|
Intinerary.LastStage << ", " <<
|
||||||
Intinerary.FirstOperandCycle << ", " <<
|
Intinerary.FirstOperandCycle << ", " <<
|
||||||
Intinerary.LastOperandCycle << " }";
|
Intinerary.LastOperandCycle << " }";
|
||||||
}
|
}
|
||||||
|
|
||||||
OS << ", // " << j << "\n";
|
OS << ", // " << j << "\n";
|
||||||
}
|
}
|
||||||
|
|
||||||
// End processor itinerary table
|
// End processor itinerary table
|
||||||
OS << " { 1, ~0U, ~0U, ~0U, ~0U } // end marker\n";
|
OS << " { 1, ~0U, ~0U, ~0U, ~0U } // end marker\n";
|
||||||
OS << "};\n";
|
OS << "};\n";
|
||||||
@ -524,7 +524,7 @@ void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
|
|||||||
OS << "\n";
|
OS << "\n";
|
||||||
OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
|
OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
|
||||||
<< "static const llvm::SubtargetInfoKV ProcItinKV[] = {\n";
|
<< "static const llvm::SubtargetInfoKV ProcItinKV[] = {\n";
|
||||||
|
|
||||||
// For each processor
|
// For each processor
|
||||||
for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
|
for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
|
||||||
// Next processor
|
// Next processor
|
||||||
@ -533,20 +533,20 @@ void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
|
|||||||
const std::string &Name = Processor->getValueAsString("Name");
|
const std::string &Name = Processor->getValueAsString("Name");
|
||||||
const std::string &ProcItin =
|
const std::string &ProcItin =
|
||||||
Processor->getValueAsDef("ProcItin")->getName();
|
Processor->getValueAsDef("ProcItin")->getName();
|
||||||
|
|
||||||
// Emit as { "cpu", procinit },
|
// Emit as { "cpu", procinit },
|
||||||
OS << " { "
|
OS << " { "
|
||||||
<< "\"" << Name << "\", "
|
<< "\"" << Name << "\", "
|
||||||
<< "(void *)&" << ProcItin;
|
<< "(void *)&" << ProcItin;
|
||||||
|
|
||||||
OS << " }";
|
OS << " }";
|
||||||
|
|
||||||
// Depending on ''if more in the list'' emit comma
|
// Depending on ''if more in the list'' emit comma
|
||||||
if (++i < N) OS << ",";
|
if (++i < N) OS << ",";
|
||||||
|
|
||||||
OS << "\n";
|
OS << "\n";
|
||||||
}
|
}
|
||||||
|
|
||||||
// End processor table
|
// End processor table
|
||||||
OS << "};\n";
|
OS << "};\n";
|
||||||
|
|
||||||
@ -566,13 +566,13 @@ void SubtargetEmitter::EmitData(raw_ostream &OS) {
|
|||||||
std::vector<Record*> ItinClassList =
|
std::vector<Record*> ItinClassList =
|
||||||
Records.getAllDerivedDefinitions("InstrItinClass");
|
Records.getAllDerivedDefinitions("InstrItinClass");
|
||||||
std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord());
|
std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord());
|
||||||
|
|
||||||
// Enumerate all the itinerary classes
|
// Enumerate all the itinerary classes
|
||||||
unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap,
|
unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap,
|
||||||
ItinClassList);
|
ItinClassList);
|
||||||
// Make sure the rest is worth the effort
|
// Make sure the rest is worth the effort
|
||||||
HasItineraries = NItinClasses != 1; // Ignore NoItinerary.
|
HasItineraries = NItinClasses != 1; // Ignore NoItinerary.
|
||||||
|
|
||||||
if (HasItineraries) {
|
if (HasItineraries) {
|
||||||
std::vector<std::vector<InstrItinerary> > ProcList;
|
std::vector<std::vector<InstrItinerary> > ProcList;
|
||||||
// Emit the stage data
|
// Emit the stage data
|
||||||
@ -594,8 +594,8 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) {
|
|||||||
Records.getAllDerivedDefinitions("SubtargetFeature");
|
Records.getAllDerivedDefinitions("SubtargetFeature");
|
||||||
std::sort(Features.begin(), Features.end(), LessRecord());
|
std::sort(Features.begin(), Features.end(), LessRecord());
|
||||||
|
|
||||||
OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
|
OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
|
||||||
<< "// subtarget options.\n"
|
<< "// subtarget options.\n"
|
||||||
<< "std::string llvm::";
|
<< "std::string llvm::";
|
||||||
OS << Target;
|
OS << Target;
|
||||||
OS << "Subtarget::ParseSubtargetFeatures(const std::string &FS,\n"
|
OS << "Subtarget::ParseSubtargetFeatures(const std::string &FS,\n"
|
||||||
@ -618,7 +618,7 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) {
|
|||||||
OS << " if ((Bits & " << Instance << ") != 0) "
|
OS << " if ((Bits & " << Instance << ") != 0) "
|
||||||
<< Attribute << " = " << Value << ";\n";
|
<< Attribute << " = " << Value << ";\n";
|
||||||
else
|
else
|
||||||
OS << " if ((Bits & " << Instance << ") != 0 && " << Attribute <<
|
OS << " if ((Bits & " << Instance << ") != 0 && " << Attribute <<
|
||||||
" < " << Value << ") " << Attribute << " = " << Value << ";\n";
|
" < " << Value << ") " << Attribute << " = " << Value << ";\n";
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -24,11 +24,11 @@
|
|||||||
namespace llvm {
|
namespace llvm {
|
||||||
|
|
||||||
class SubtargetEmitter : public TableGenBackend {
|
class SubtargetEmitter : public TableGenBackend {
|
||||||
|
|
||||||
RecordKeeper &Records;
|
RecordKeeper &Records;
|
||||||
std::string Target;
|
std::string Target;
|
||||||
bool HasItineraries;
|
bool HasItineraries;
|
||||||
|
|
||||||
void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
|
void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
|
||||||
void FeatureKeyValues(raw_ostream &OS);
|
void FeatureKeyValues(raw_ostream &OS);
|
||||||
void CPUKeyValues(raw_ostream &OS);
|
void CPUKeyValues(raw_ostream &OS);
|
||||||
@ -52,7 +52,7 @@ class SubtargetEmitter : public TableGenBackend {
|
|||||||
void EmitProcessorLookup(raw_ostream &OS);
|
void EmitProcessorLookup(raw_ostream &OS);
|
||||||
void EmitData(raw_ostream &OS);
|
void EmitData(raw_ostream &OS);
|
||||||
void ParseFeaturesFunction(raw_ostream &OS);
|
void ParseFeaturesFunction(raw_ostream &OS);
|
||||||
|
|
||||||
public:
|
public:
|
||||||
SubtargetEmitter(RecordKeeper &R) : Records(R), HasItineraries(false) {}
|
SubtargetEmitter(RecordKeeper &R) : Records(R), HasItineraries(false) {}
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user