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Make simplifycfg reprocess newly formed "br (cond1 | cond2)" conditions
when simplifying, allowing them to be eagerly turned into switches. This is the last step required to get "Example 7" from this blog post: http://blog.regehr.org/archives/320 On X86, we now generate this machine code, which (to my eye) seems better than the ICC generated code: _crud: ## @crud ## BB#0: ## %entry cmpb $33, %dil jb LBB0_4 ## BB#1: ## %switch.early.test addb $-34, %dil cmpb $58, %dil ja LBB0_3 ## BB#2: ## %switch.early.test movzbl %dil, %eax movabsq $288230376537592865, %rcx ## imm = 0x400000017001421 btq %rax, %rcx jb LBB0_4 LBB0_3: ## %lor.rhs xorl %eax, %eax ret LBB0_4: ## %lor.end movl $1, %eax ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121690 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1357,7 +1357,7 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI) {
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// must be at the front of the block.
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BasicBlock::iterator FrontIt = BB->front();
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// Ignore dbg intrinsics.
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while(isa<DbgInfoIntrinsic>(FrontIt))
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while (isa<DbgInfoIntrinsic>(FrontIt))
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++FrontIt;
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// Allow a single instruction to be hoisted in addition to the compare
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@ -1441,7 +1441,7 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI) {
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UsedValues.erase(Pair.first);
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if (UsedValues.empty()) break;
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if (Instruction* I = dyn_cast<Instruction>(Pair.first)) {
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if (Instruction *I = dyn_cast<Instruction>(Pair.first)) {
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for (Instruction::op_iterator OI = I->op_begin(), OE = I->op_end();
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OI != OE; ++OI)
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Worklist.push_back(std::make_pair(OI->get(), Pair.second+1));
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@ -1469,9 +1469,16 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI) {
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// If we need to invert the condition in the pred block to match, do so now.
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if (InvertPredCond) {
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Value *NewCond =
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BinaryOperator::CreateNot(PBI->getCondition(),
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Value *NewCond = PBI->getCondition();
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if (NewCond->hasOneUse() && isa<CmpInst>(NewCond)) {
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CmpInst *CI = cast<CmpInst>(NewCond);
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CI->setPredicate(CI->getInversePredicate());
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} else {
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NewCond = BinaryOperator::CreateNot(NewCond,
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PBI->getCondition()->getName()+".not", PBI);
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}
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PBI->setCondition(NewCond);
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BasicBlock *OldTrue = PBI->getSuccessor(0);
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BasicBlock *OldFalse = PBI->getSuccessor(1);
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@ -1507,7 +1514,7 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI) {
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AddPredecessorToBlock(FalseDest, PredBlock, BB);
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PBI->setSuccessor(1, FalseDest);
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}
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return true;
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return SimplifyCFG(PBI->getParent()) | true;
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}
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return false;
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}
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@ -203,5 +203,70 @@ if.end: ; preds = %entry
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; CHECK: i8 97, label %if.then
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; CHECK: ]
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; CHECK: %A = phi i32 [ 0, %entry ], [ 42, %switch.early.test ], [ 42, %N ], [ 42, %switch.early.test ]
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}
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define i32 @test9(i8 zeroext %c) nounwind ssp noredzone {
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entry:
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%cmp = icmp ult i8 %c, 33
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br i1 %cmp, label %lor.end, label %lor.lhs.false
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lor.lhs.false: ; preds = %entry
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%cmp4 = icmp eq i8 %c, 46
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br i1 %cmp4, label %lor.end, label %lor.lhs.false6
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lor.lhs.false6: ; preds = %lor.lhs.false
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%cmp9 = icmp eq i8 %c, 44
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br i1 %cmp9, label %lor.end, label %lor.lhs.false11
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lor.lhs.false11: ; preds = %lor.lhs.false6
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%cmp14 = icmp eq i8 %c, 58
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br i1 %cmp14, label %lor.end, label %lor.lhs.false16
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lor.lhs.false16: ; preds = %lor.lhs.false11
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%cmp19 = icmp eq i8 %c, 59
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br i1 %cmp19, label %lor.end, label %lor.lhs.false21
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lor.lhs.false21: ; preds = %lor.lhs.false16
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%cmp24 = icmp eq i8 %c, 60
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br i1 %cmp24, label %lor.end, label %lor.lhs.false26
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lor.lhs.false26: ; preds = %lor.lhs.false21
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%cmp29 = icmp eq i8 %c, 62
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br i1 %cmp29, label %lor.end, label %lor.lhs.false31
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lor.lhs.false31: ; preds = %lor.lhs.false26
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%cmp34 = icmp eq i8 %c, 34
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br i1 %cmp34, label %lor.end, label %lor.lhs.false36
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lor.lhs.false36: ; preds = %lor.lhs.false31
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%cmp39 = icmp eq i8 %c, 92
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br i1 %cmp39, label %lor.end, label %lor.rhs
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lor.rhs: ; preds = %lor.lhs.false36
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%cmp43 = icmp eq i8 %c, 39
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br label %lor.end
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lor.end: ; preds = %lor.rhs, %lor.lhs.false36, %lor.lhs.false31, %lor.lhs.false26, %lor.lhs.false21, %lor.lhs.false16, %lor.lhs.false11, %lor.lhs.false6, %lor.lhs.false, %entry
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%0 = phi i1 [ true, %lor.lhs.false36 ], [ true, %lor.lhs.false31 ], [ true, %lor.lhs.false26 ], [ true, %lor.lhs.false21 ], [ true, %lor.lhs.false16 ], [ true, %lor.lhs.false11 ], [ true, %lor.lhs.false6 ], [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp43, %lor.rhs ]
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%conv46 = zext i1 %0 to i32
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ret i32 %conv46
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; CHECK: @test9
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; CHECK: %cmp = icmp ult i8 %c, 33
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; CHECK: br i1 %cmp, label %lor.end, label %switch.early.test
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; CHECK: switch.early.test:
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; CHECK: switch i8 %c, label %lor.rhs [
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; CHECK: i8 46, label %lor.end
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; CHECK: i8 44, label %lor.end
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; CHECK: i8 58, label %lor.end
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; CHECK: i8 59, label %lor.end
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; CHECK: i8 60, label %lor.end
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; CHECK: i8 62, label %lor.end
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; CHECK: i8 34, label %lor.end
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; CHECK: i8 92, label %lor.end
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; CHECK: i8 39, label %lor.end
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; CHECK: ]
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}
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