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This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190152 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vladimir Medic 2013-09-06 12:53:21 +00:00
parent 9e935a77a5
commit dadd1fba32
6 changed files with 68 additions and 8 deletions
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24
lib/Target/Mips/MicroMipsInstrFormats.td
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@ -138,3 +138,27 @@ class CMov_F_I_FM_MM<bits<7> func> : MMArch {
let Inst{12-6} = func;
let Inst{5-0} = 0x3b;
}
class MTLO_FM_MM<bits<10> funct> : MMArch {
bits<5> rs;
bits<32> Inst;
let Inst{31-26} = 0x00;
let Inst{25-21} = 0x00;
let Inst{20-16} = rs;
let Inst{15-6} = funct;
let Inst{5-0} = 0x3c;
}
class MFLO_FM_MM<bits<10> funct> : MMArch {
bits<5> rd;
bits<32> Inst;
let Inst{31-26} = 0x00;
let Inst{25-21} = 0x00;
let Inst{20-16} = rd;
let Inst{15-6} = funct;
let Inst{5-0} = 0x3c;
}

10
lib/Target/Mips/MicroMipsInstrInfo.td
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@ -119,4 +119,14 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
CMov_F_I_FM_MM<0x25>;
def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, IIAlu>,
CMov_F_I_FM_MM<0x5>;
/// Move to/from HI/LO
def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
MTLO_FM_MM<0x0b5>;
def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
MTLO_FM_MM<0x0f5>;
def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, [HI0]>,
MFLO_FM_MM<0x035>;
def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>,
MFLO_FM_MM<0x075>;
}

4
lib/Target/Mips/MipsInstrFormats.td
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@ -321,7 +321,7 @@ class SLTI_FM<bits<6> op> : StdArch {
let Inst{15-0} = imm16;
}
class MFLO_FM<bits<6> funct> {
class MFLO_FM<bits<6> funct> : StdArch {
bits<5> rd;
bits<32> Inst;
@ -333,7 +333,7 @@ class MFLO_FM<bits<6> funct> {
let Inst{5-0} = funct;
}
class MTLO_FM<bits<6> funct> {
class MTLO_FM<bits<6> funct> : StdArch {
bits<5> rs;
bits<32> Inst;

14
lib/Target/Mips/MipsInstrInfo.td
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@ -690,13 +690,15 @@ class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
// Move from Hi/Lo
class MoveFromLOHI<string opstr, RegisterOperand RO, list<Register> UseRegs>:
InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo,
FrmR, opstr> {
let Uses = UseRegs;
let neverHasSideEffects = 1;
}
class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo,
FrmR, opstr> {
let Defs = DefRegs;
let neverHasSideEffects = 1;
}
@ -1016,10 +1018,10 @@ def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
0, 1, 1>;
def MTHI : MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
def MTLO : MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
def MFHI : MoveFromLOHI<"mfhi", GPR32Opnd, [HI0]>, MFLO_FM<0x10>;
def MFLO : MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>, MFLO_FM<0x12>;
def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, [HI0]>, MFLO_FM<0x10>;
def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>, MFLO_FM<0x12>;
/// Sign Ext In Register Instructions.
def SEB : SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>;

12
test/MC/Disassembler/Mips/micromips.txt
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@ -159,3 +159,15 @@
# CHECK: movf $9, $6, $fcc0
0x55 0x26 0x01 0x7b
# CHECK: mthi $6
0x00 0x06 0x2d 0x7c
# CHECK: mfhi $6
0x00 0x06 0x0d 0x7c
# CHECK: mtlo $6
0x00 0x06 0x3d 0x7c
# CHECK: mflo $6
0x00 0x06 0x1d 0x7c

12
test/MC/Disassembler/Mips/micromips_le.txt
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@ -159,3 +159,15 @@
# CHECK: movf $9, $6, $fcc0
0x26 0x55 0x7b 0x01
# CHECK: mthi $6
0x06 0x00 0x7c 0x2d
# CHECK: mfhi $6
0x06 0x00 0x7c 0x0d
# CHECK: mtlo $6
0x06 0x00 0x7c 0x3d
# CHECK: mflo $6
0x06 0x00 0x7c 0x1d