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ARM: support FK_SecRel_2 relocations on WoA

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This adds FK_SecRel_2 relocation support to ARM.  This enables the building of
object files for armv7-windows-msvc which enables CodeView line tables for
debugging as opposed to armv7-windows-itanium which currently uses DWARF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208273 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Saleem Abdulrasool 2014-05-08 01:35:57 +00:00
parent 4983b992ab
commit dade1d5db5
3 changed files with 30 additions and 14 deletions
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4
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
View File

@ -344,6 +344,8 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
case FK_Data_2:
case FK_Data_4:
return Value;
case FK_SecRel_2:
return Value;
case FK_SecRel_4:
return Value;
case ARM::fixup_arm_movt_hi16:
@ -674,6 +676,8 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
case ARM::fixup_t2_movw_lo16:
return 4;
case FK_SecRel_2:
return 2;
case FK_SecRel_4:
return 4;
}

2
lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp
View File

@ -49,6 +49,8 @@ unsigned ARMWinCOFFObjectWriter::getRelocType(const MCValue &Target,
default:
return COFF::IMAGE_REL_ARM_ADDR32;
}
case FK_SecRel_2:
return COFF::IMAGE_REL_ARM_SECTION;
case FK_SecRel_4:
return COFF::IMAGE_REL_ARM_SECREL;
case ARM::fixup_t2_condbranch:

38
test/MC/ARM/coff-debugging-secrel.ll
View File

@ -1,5 +1,8 @@
; RUN: llc -mtriple thumbv7--windows-itanium -filetype obj -o - %s \
; RUN: | llvm-readobj -r - | FileCheck %s
; RUN: | llvm-readobj -r - | FileCheck %s -check-prefix CHECK-ITANIUM
; RUN: llc -mtriple thumbv7--windows-msvc -filetype obj -o - %s \
; RUN: | llvm-readobj -r - | Filecheck %s -check-prefix CHECK-MSVC
; ModuleID = '/Users/compnerd/work/llvm/test/MC/ARM/reduced.c'
target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64"
@ -25,17 +28,24 @@ entry:
!9 = metadata !{i32 2, metadata !"Dwarf Version", i32 4}
!10 = metadata !{i32 1, metadata !"Debug Info Version", i32 1}
; CHECK: Relocations [
; CHECK: Section {{.*}} .debug_info {
; CHECK: 0x6 IMAGE_REL_ARM_SECREL .debug_abbrev
; CHECK: 0xC IMAGE_REL_ARM_SECREL .debug_str
; CHECK: 0x12 IMAGE_REL_ARM_SECREL .debug_str
; CHECK: 0x16 IMAGE_REL_ARM_SECREL .debug_line
; CHECK: 0x1A IMAGE_REL_ARM_SECREL .debug_str
; CHECK: 0x27 IMAGE_REL_ARM_SECREL .debug_str
; CHECK: }
; CHECK: Section {{.*}}.debug_pubnames {
; CHECK: 0x6 IMAGE_REL_ARM_SECREL .debug_info
; CHECK: }
; CHECK: ]
; CHECK-ITANIUM: Relocations [
; CHECK-ITANIUM: Section {{.*}} .debug_info {
; CHECK-ITANIUM: 0x6 IMAGE_REL_ARM_SECREL .debug_abbrev
; CHECK-ITANIUM: 0xC IMAGE_REL_ARM_SECREL .debug_str
; CHECK-ITANIUM: 0x12 IMAGE_REL_ARM_SECREL .debug_str
; CHECK-ITANIUM: 0x16 IMAGE_REL_ARM_SECREL .debug_line
; CHECK-ITANIUM: 0x1A IMAGE_REL_ARM_SECREL .debug_str
; CHECK-ITANIUM: 0x27 IMAGE_REL_ARM_SECREL .debug_str
; CHECK-ITANIUM: }
; CHECK-ITANIUM: Section {{.*}}.debug_pubnames {
; CHECK-ITANIUM: 0x6 IMAGE_REL_ARM_SECREL .debug_info
; CHECK-ITANIUM: }
; CHECK-ITANIUM: ]
; CHECK-MSVC: Relocations [
; CHECK-MSVC: Section {{.*}} .debug$S {
; CHECK-MSVC: 0xC IMAGE_REL_ARM_SECREL function
; CHECK-MSVC: 0x10 IMAGE_REL_ARM_SECTION function
; CHECK-MSVC: }
; CHECK-MSVC: ]