mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 04:29:21 +00:00
* Broke up SparcV9.td into separate files as it was getting unmanageable
* Added some Format 4 classes, but not instructions * Added notes on missing sections with FIXMEs * Added RDCCR instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6388 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
parent
8e5bf70dff
commit
dafa504341
@ -2,53 +2,12 @@
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// vim:ft=cpp
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-Independent interface
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//===----------------------------------------------------------------------===//
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class Register {
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string Namespace = "";
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int Size;
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}
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class Instruction {
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string Name; // The opcode string for this instruction
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string Namespace = "";
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list<Register> Uses = []; // Default to using no non-operand registers
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list<Register> Defs = []; // Default to modifying no non-operand registers
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// These bits capture information about the high-level semantics of the
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// instruction.
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bit isReturn = 0; // Is this instruction a return instruction?
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bit isBranch = 0; // Is this instruction a branch instruction?
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bit isCall = 0; // Is this instruction a call instruction?
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}
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#include "../Target.td"
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#include "SparcV9_Reg.td"
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//===----------------------------------------------------------------------===//
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// Declarations that describe the Sparc register file
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//===----------------------------------------------------------------------===//
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class V9Reg : Register { set Namespace = "SparcV9"; }
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// Ri - One of the 32 64 bit integer registers
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class Ri<bits<5> num> : V9Reg { set Size = 64; field bits<5> Num = num; }
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def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>;
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def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>;
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def O0 : Ri< 8>; def O1 : Ri< 9>; def O2 : Ri<10>; def O3 : Ri<11>;
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def O4 : Ri<12>; def O5 : Ri<13>; def O6 : Ri<14>; def O7 : Ri<15>;
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def L0 : Ri<16>; def L1 : Ri<17>; def L2 : Ri<18>; def L3 : Ri<19>;
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def L4 : Ri<20>; def L5 : Ri<21>; def L6 : Ri<22>; def L7 : Ri<23>;
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def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>;
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def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>;
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// Floating-point registers?
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// ...
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//===----------------------------------------------------------------------===//
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// This is temporary testing stuff.....
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// Instructions
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//===----------------------------------------------------------------------===//
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class InstV9 : Instruction { // Sparc instruction baseline
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@ -65,219 +24,9 @@ class InstV9 : Instruction { // Sparc instruction baseline
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bit isPrivileged = 0; // Is this a privileged instruction?
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}
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//===----------------------------------------------------------------------===//
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// Format #2 classes
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//
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class F2 : InstV9 { // Format 2 instructions
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bits<3> op2;
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set op = 0; // Op = 0
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set Inst{24-22} = op2;
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}
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// Format 2.1 instructions
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class F2_1<string name> : F2 {
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bits<5> rd;
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bits<22> imm;
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set Name = name;
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set Inst{29-25} = rd;
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set Inst{21-0} = imm;
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}
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class F2_br : F2 { // Format 2 Branch instruction
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bit annul; // All branches have an annul bit
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set Inst{29} = annul;
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set isBranch = 1; // All instances are branch instructions
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}
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class F2_2<bits<4> cond, string name> : F2_br { // Format 2.2 instructions
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bits<22> disp;
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set Name = name;
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set Inst{28-25} = cond;
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set Inst{21-0} = disp;
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}
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class F2_3<bits<4> cond, string name> : F2_br { // Format 2.3 instructions
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bits<2> cc;
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bits<19> disp;
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bit predict;
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set Name = name;
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set Inst{28-25} = cond;
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set Inst{21-20} = cc;
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set Inst{19} = predict;
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set Inst{18-0} = disp;
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}
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class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions
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// Variables exposed by the instruction...
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bit predict;
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bits<5> rs1;
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bits<16> disp;
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set Name = name;
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set Inst{28} = 0;
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set Inst{27-25} = rcond;
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// Inst{24-22} = op2 field
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set Inst{21-20} = disp{15-14};
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set Inst{19} = predict;
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set Inst{18-14} = rs1;
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set Inst{13-0 } = disp{13-0};
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}
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//===----------------------------------------------------------------------===//
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// Format #3 classes
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//
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// F3 - Common superclass of all F3 instructions. All instructions have an op3
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// field.
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class F3 : InstV9 {
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bits<6> op3;
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set op{1} = 1; // Op = 2 or 3
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set Inst{24-19} = op3;
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}
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class F3_rd : F3 {
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bits<5> rd;
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set Inst{29-25} = rd;
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}
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class F3_rdsimm13 : F3_rd {
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bits<13> simm13;
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set Inst{12-0} = simm13;
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}
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class F3_rdsimm13rs1 : F3_rdsimm13 {
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bits<5> rs1;
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set Inst{18-14} = rs1;
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}
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// F3_rdrs1 - Common superclass of instructions that use rd & rs1
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class F3_rdrs1 : F3_rd {
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bits<5> rs1;
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set Inst{18-14} = rs1;
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}
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// F3_rs1rdrs2 - Common superclass of instructions with rd, rs1, & rs2 fields
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class F3_rdrs1rs2 : F3_rdrs1 {
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bits<5> rs2;
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set Inst{4-0} = rs2;
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}
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// F3_rs1 - Common class of instructions that do not have an rd field,
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// but start at rs1
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class F3_rs1 : F3 {
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bits<5> rs1;
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//set Inst{29-25} = dontcare;
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set Inst{18-14} = rs1;
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}
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// F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
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class F3_rs1rs2 : F3_rs1 {
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bits<5> rs2;
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//set Inst{12-5} = dontcare;
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set Inst{4-0} = rs2;
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}
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// F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
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class F3_rs1simm13 : F3_rs1 {
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bits<13> simm13;
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set Inst{12-0} = simm13;
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}
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// Specific F3 classes...
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//
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class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
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set op = opVal;
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set op3 = op3val;
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set Name = name;
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set Inst{13} = 0; // i field = 0
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//set Inst{12-5} = dontcare;
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}
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class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rdsimm13rs1 {
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set op = opVal;
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set op3 = op3val;
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set Name = name;
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set Inst{13} = 1; // i field = 1
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}
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class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
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set op = opVal;
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set op3 = op3val;
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set Name = name;
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set Inst{13} = 0;
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}
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class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1simm13 {
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bits<13> simm;
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set op = opVal;
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set op3 = op3Val;
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set Name = name;
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//set Inst{29-25} = dontcare;
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set Inst{13} = 1;
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set Inst{12-0} = simm;
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}
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class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1rs2 {
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bit x;
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set op = opVal;
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set op3 = op3Val;
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set Name = name;
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set Inst{13} = 0; // i field = 0
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set Inst{12} = x;
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//set Inst{11-5} = dontcare;
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}
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class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3 {
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bits<5> shcnt;
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set Name = name;
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set Inst{13} = 1; // i field = 1
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set Inst{12} = 0; // x field = 0
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//set Inst{11-5} = dontcare;
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set Inst{4-0} = shcnt;
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}
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class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3 {
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bits<6> shcnt;
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set Name = name;
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set Inst{13} = 1; // i field = 1
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set Inst{12} = 1; // x field = 1
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//set Inst{11-6} = dontcare;
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set Inst{5-0} = shcnt;
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}
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class F3_14<bits<2> opVal, bits<6> op3val,
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bits<9> opfval, string name> : F3_rdrs1rs2 {
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set op = opVal;
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set op3 = op3val;
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set Name = name;
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//set Inst{18-14} = dontcare;
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set Inst{13-5} = opfval;
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}
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class F3_16<bits<2> opVal, bits<6> op3val,
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bits<9> opfval, string name> : F3_rdrs1rs2 {
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set op = opVal;
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set op3 = op3val;
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set Name = name;
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set Inst{13-5} = opfval;
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}
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class F3_18<bits<5> fcn, string name> : F3 {
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set op = 2;
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set op3 = 0b111110;
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set Name = name;
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set Inst{29-25} = fcn;
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//set Inst{18-0 } = dontcare;
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}
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#include "SparcV9_F2.td"
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#include "SparcV9_F3.td"
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#include "SparcV9_F4.td"
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//===----------------------------------------------------------------------===//
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// Instruction list...
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@ -570,6 +319,12 @@ def FMOVFULE : F4_7<2, 0b110101, 0b1110, "fmovfule">; // fmovfule r, r
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def FMOVFO : F4_7<2, 0b110101, 0b1111, "fmovfo">; // fmovfo r, r
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#endif
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// Section A.34: Move F-P Register on Integer Register (FMOVr)
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// Section A.35: Move Integer Register on Condition (MOVcc)
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// Section A.36: Move Integer Register on Register Condition (MOVR)
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// Section A.37: Multiply and Divide (64-bit) - p199
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def MULXr : F3_1<2, 0b001001, "mulx">; // mulx r, r, r
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def SDIVXr : F3_1<2, 0b101101, "sdivx">; // mulx r, r, r
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@ -593,6 +348,8 @@ def UDIVXi : F3_2<2, 0b001101, "udivx">; // mulx r, i, r
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// def SMULCCi : F3_1<2, 0b011011, "smulcc">; // smulcc r, i, r
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//}
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// Section A.39: FIXME
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// Section A.40: No operation - p204
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// NOP is really a pseudo-instruction (special case of SETHI)
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set op2 = 0b100 in {
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@ -603,6 +360,16 @@ set op2 = 0b100 in {
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}
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}
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// Section A.41: FIXME
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// Section A.42: FIXME
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// Section A.43: FIXME
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// Section A.44: Read State Register
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// The only instr from this section currently used is RDCCR
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set rs1 = 2 in {
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def RDCCR : F3_17<2, 0b101000, "rd">; // rd %ccr, r
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}
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// Section A.45: RETURN - p216
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set isReturn = 1 in {
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def RETURNr : F3_3<2, 0b111001, "return">; // return
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@ -616,7 +383,7 @@ def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r
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def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r
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// Section A.47: SAVED and RESTORED - p219
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// FIXME: add these instrs
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// Not currently used in Sparc backend
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// Section A.48: SETHI - p220
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set op2 = 0b100 in {
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@ -657,6 +424,9 @@ def SLLXi6 : F3_13<2, 0b100101, "sllx">; // sllx r, shcnt64, r
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def SRLXi6 : F3_13<2, 0b100110, "srlx">; // srlx r, shcnt64, r
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def SRAXi6 : F3_13<2, 0b100111, "srax">; // srax r, shcnt64, r
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// Section A.50: FIXME
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// Section A.51: FIXME
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// Section A.52: Store Floating-point -p225
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def STFr : F3_1<3, 0b100100, "st">; // st r, [r+r]
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def STFi : F3_2<3, 0b100100, "st">; // st r, [r+i]
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@ -672,6 +442,8 @@ set isDeprecated = 1 in {
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def STXFSRr : F3_1<3, 0b100101, "stq">; // stx r, [r+r]
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def STXFSRi : F3_2<3, 0b100101, "stq">; // stx r, [r+i]
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// Section A.53: FIXME
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// Section A.54: Store Integer - p229
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def STBr : F3_1<3, 0b000101, "stb">; // stb r, [r+r]
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def STBi : F3_2<3, 0b000101, "stb">; // stb r, [r+i]
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@ -683,6 +455,7 @@ def STXr : F3_1<3, 0b001110, "stb">; // stb r, [r+r]
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def STXi : F3_2<3, 0b001110, "stb">; // stb r, [r+i]
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// Floating point store...
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// Section A.55: FIXME
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// Section A.56: Subtract - p233
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def SUBr : F3_1<2, 0b000100, "sub">; // sub r, r, r
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@ -693,3 +466,5 @@ def SUBCr : F3_1<2, 0b001100, "subc">; // subc r, r, r
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def SUBCi : F3_1<2, 0b001100, "subc">; // subc r, i, r
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def SUBCccr : F3_1<2, 0b011100, "subccc">; // subccc r, r, r
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def SUBCcci : F3_1<2, 0b011100, "subccc">; // subccc r, i, r
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// FIXME: More...?
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64
lib/Target/SparcV9/SparcV9_F2.td
Normal file
64
lib/Target/SparcV9/SparcV9_F2.td
Normal file
@ -0,0 +1,64 @@
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//===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
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// vim:ft=cpp
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Format #2 classes
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//
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class F2 : InstV9 { // Format 2 instructions
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bits<3> op2;
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set op = 0; // Op = 0
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set Inst{24-22} = op2;
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}
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// Format 2.1 instructions
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class F2_1<string name> : F2 {
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bits<5> rd;
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bits<22> imm;
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set Name = name;
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set Inst{29-25} = rd;
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set Inst{21-0} = imm;
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}
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class F2_br : F2 { // Format 2 Branch instruction
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bit annul; // All branches have an annul bit
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set Inst{29} = annul;
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set isBranch = 1; // All instances are branch instructions
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}
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class F2_2<bits<4> cond, string name> : F2_br { // Format 2.2 instructions
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bits<22> disp;
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set Name = name;
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set Inst{28-25} = cond;
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set Inst{21-0} = disp;
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}
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class F2_3<bits<4> cond, string name> : F2_br { // Format 2.3 instructions
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bits<2> cc;
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bits<19> disp;
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bit predict;
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set Name = name;
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set Inst{28-25} = cond;
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set Inst{21-20} = cc;
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set Inst{19} = predict;
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set Inst{18-0} = disp;
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}
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class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions
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// Variables exposed by the instruction...
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bit predict;
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bits<5> rs1;
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bits<16> disp;
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set Name = name;
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set Inst{28} = 0;
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set Inst{27-25} = rcond;
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// Inst{24-22} = op2 field
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set Inst{21-20} = disp{15-14};
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set Inst{19} = predict;
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set Inst{18-14} = rs1;
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set Inst{13-0 } = disp{13-0};
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}
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171
lib/Target/SparcV9/SparcV9_F3.td
Normal file
171
lib/Target/SparcV9/SparcV9_F3.td
Normal file
@ -0,0 +1,171 @@
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//===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
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// vim:ft=cpp
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Format #3 classes
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//
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||||
|
||||
// F3 - Common superclass of all F3 instructions. All instructions have an op3
|
||||
// field.
|
||||
class F3 : InstV9 {
|
||||
bits<6> op3;
|
||||
set op{1} = 1; // Op = 2 or 3
|
||||
set Inst{24-19} = op3;
|
||||
}
|
||||
|
||||
class F3_rd : F3 {
|
||||
bits<5> rd;
|
||||
set Inst{29-25} = rd;
|
||||
}
|
||||
|
||||
class F3_rdsimm13 : F3_rd {
|
||||
bits<13> simm13;
|
||||
set Inst{12-0} = simm13;
|
||||
}
|
||||
|
||||
class F3_rdsimm13rs1 : F3_rdsimm13 {
|
||||
bits<5> rs1;
|
||||
set Inst{18-14} = rs1;
|
||||
}
|
||||
|
||||
// F3_rdrs1 - Common superclass of instructions that use rd & rs1
|
||||
class F3_rdrs1 : F3_rd {
|
||||
bits<5> rs1;
|
||||
set Inst{18-14} = rs1;
|
||||
}
|
||||
|
||||
// F3_rs1rdrs2 - Common superclass of instructions with rd, rs1, & rs2 fields
|
||||
class F3_rdrs1rs2 : F3_rdrs1 {
|
||||
bits<5> rs2;
|
||||
set Inst{4-0} = rs2;
|
||||
}
|
||||
|
||||
// F3_rs1 - Common class of instructions that do not have an rd field,
|
||||
// but start at rs1
|
||||
class F3_rs1 : F3 {
|
||||
bits<5> rs1;
|
||||
//set Inst{29-25} = dontcare;
|
||||
set Inst{18-14} = rs1;
|
||||
}
|
||||
|
||||
// F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
|
||||
class F3_rs1rs2 : F3_rs1 {
|
||||
bits<5> rs2;
|
||||
//set Inst{12-5} = dontcare;
|
||||
set Inst{4-0} = rs2;
|
||||
}
|
||||
|
||||
// F3_rs1simm13 - Common class of instructions that only have rs1 and simm13
|
||||
class F3_rs1simm13 : F3_rs1 {
|
||||
bits<13> simm13;
|
||||
set Inst{12-0} = simm13;
|
||||
}
|
||||
|
||||
|
||||
// Specific F3 classes...
|
||||
//
|
||||
|
||||
class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
|
||||
set op = opVal;
|
||||
set op3 = op3val;
|
||||
set Name = name;
|
||||
set Inst{13} = 0; // i field = 0
|
||||
//set Inst{12-5} = dontcare;
|
||||
}
|
||||
|
||||
class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rdsimm13rs1 {
|
||||
set op = opVal;
|
||||
set op3 = op3val;
|
||||
set Name = name;
|
||||
set Inst{13} = 1; // i field = 1
|
||||
}
|
||||
|
||||
class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
|
||||
set op = opVal;
|
||||
set op3 = op3val;
|
||||
set Name = name;
|
||||
set Inst{13} = 0;
|
||||
}
|
||||
|
||||
class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1simm13 {
|
||||
bits<13> simm;
|
||||
set op = opVal;
|
||||
set op3 = op3Val;
|
||||
set Name = name;
|
||||
//set Inst{29-25} = dontcare;
|
||||
set Inst{13} = 1;
|
||||
set Inst{12-0} = simm;
|
||||
}
|
||||
|
||||
class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1rs2 {
|
||||
bit x;
|
||||
set op = opVal;
|
||||
set op3 = op3Val;
|
||||
set Name = name;
|
||||
set Inst{13} = 0; // i field = 0
|
||||
set Inst{12} = x;
|
||||
//set Inst{11-5} = dontcare;
|
||||
}
|
||||
|
||||
class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3 {
|
||||
bits<5> shcnt;
|
||||
|
||||
set Name = name;
|
||||
set Inst{13} = 1; // i field = 1
|
||||
set Inst{12} = 0; // x field = 0
|
||||
//set Inst{11-5} = dontcare;
|
||||
set Inst{4-0} = shcnt;
|
||||
}
|
||||
|
||||
class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3 {
|
||||
bits<6> shcnt;
|
||||
|
||||
set Name = name;
|
||||
set Inst{13} = 1; // i field = 1
|
||||
set Inst{12} = 1; // x field = 1
|
||||
//set Inst{11-6} = dontcare;
|
||||
set Inst{5-0} = shcnt;
|
||||
}
|
||||
|
||||
class F3_14<bits<2> opVal, bits<6> op3Val,
|
||||
bits<9> opfval, string name> : F3_rdrs1rs2 {
|
||||
set op = opVal;
|
||||
set op3 = op3Val;
|
||||
set Name = name;
|
||||
//set Inst{18-14} = dontcare;
|
||||
set Inst{13-5} = opfval;
|
||||
}
|
||||
|
||||
class F3_16<bits<2> opVal, bits<6> op3Val,
|
||||
bits<9> opfval, string name> : F3_rdrs1rs2 {
|
||||
set op = opVal;
|
||||
set op3 = op3Val;
|
||||
set Name = name;
|
||||
set Inst{13-5} = opfval;
|
||||
}
|
||||
|
||||
class F3_17<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1 {
|
||||
set op = opVal;
|
||||
set op3 = op3Val;
|
||||
set Name = name;
|
||||
//Inst{13-0} = dontcare;
|
||||
}
|
||||
|
||||
class F3_18<bits<5> fcn, string name> : F3 {
|
||||
set op = 2;
|
||||
set op3 = 0b111110;
|
||||
set Name = name;
|
||||
set Inst{29-25} = fcn;
|
||||
//set Inst{18-0 } = dontcare;
|
||||
}
|
||||
|
||||
class F3_19<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
|
||||
set op = opVal;
|
||||
set op3 = op3Val;
|
||||
set Name = name;
|
||||
//Inst{18-0} = dontcare;
|
||||
}
|
||||
|
||||
// FIXME: class F3_20
|
||||
// FIXME: class F3_21
|
||||
90
lib/Target/SparcV9/SparcV9_F4.td
Normal file
90
lib/Target/SparcV9/SparcV9_F4.td
Normal file
@ -0,0 +1,90 @@
|
||||
//===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
|
||||
// vim:ft=cpp
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//----------------------- F4 classes -----------------------------------------
|
||||
|
||||
// F4 - Common superclass of all F4 instructions. All instructions have an op3
|
||||
// field.
|
||||
class F4 : InstV9 {
|
||||
bits<6> op3;
|
||||
set Inst{24-19} = op3;
|
||||
}
|
||||
|
||||
class F4_rd : F4 {
|
||||
bits<5> rd;
|
||||
set Inst{29-25} = rd;
|
||||
}
|
||||
|
||||
class F4_rdsimm11 : F4_rd {
|
||||
bits<11> simm11;
|
||||
set Inst{10-0} = simm11;
|
||||
}
|
||||
|
||||
class F4_rdsimm11rs1 : F4_rdsimm11 {
|
||||
bits<5> rs1;
|
||||
set Inst{18-14} = rs1;
|
||||
}
|
||||
|
||||
// F4_rdrs1 - Common superclass of instructions that use rd & rs1
|
||||
class F4_rdrs1 : F4_rd {
|
||||
bits<5> rs1;
|
||||
set Inst{18-14} = rs1;
|
||||
}
|
||||
|
||||
// F4_rs1rdrs2 - Common superclass of instructions with rd, rs1, & rs2 fields
|
||||
class F4_rdrs1rs2 : F4_rdrs1 {
|
||||
bits<5> rs2;
|
||||
set Inst{4-0} = rs2;
|
||||
}
|
||||
|
||||
// F4_rs1 - Common class of instructions that do not have an rd field,
|
||||
// but start at rs1
|
||||
class F4_rs1 : F4 {
|
||||
bits<5> rs1;
|
||||
//set Inst{29-25} = dontcare;
|
||||
set Inst{18-14} = rs1;
|
||||
}
|
||||
|
||||
// F4_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
|
||||
class F4_rs1rs2 : F4_rs1 {
|
||||
bits<5> rs2;
|
||||
//set Inst{12-5} = dontcare;
|
||||
set Inst{4-0} = rs2;
|
||||
}
|
||||
|
||||
// Actual F4 instruction classes
|
||||
|
||||
class F4_1<bits<2> opVal, bits<6> op3Val, string name> : F4_rdrs1rs2 {
|
||||
bits<2> cc;
|
||||
|
||||
set op = opVal;
|
||||
set op3 = op3Val;
|
||||
set Name = name;
|
||||
set Inst{13} = 0; // i bit
|
||||
set Inst{12-11} = cc;
|
||||
//set Inst{10-5} = dontcare;
|
||||
}
|
||||
|
||||
class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rdsimm11rs1 {
|
||||
bits<2> cc;
|
||||
|
||||
set op = opVal;
|
||||
set op3 = op3Val;
|
||||
set Name = name;
|
||||
set Inst{13} = 1; // i bit
|
||||
set Inst{12-11} = cc;
|
||||
}
|
||||
|
||||
class F4_3<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
|
||||
bits<5> rs2;
|
||||
bits<2> cc;
|
||||
|
||||
set op = opVal;
|
||||
set op3 = op3Val;
|
||||
set Name = name;
|
||||
set Inst{13} = 0; // i bit
|
||||
set Inst{12-11} = cc;
|
||||
//set Inst{10-5} = dontcare;
|
||||
set Inst{4-0} = rs2;
|
||||
}
|
||||
23
lib/Target/SparcV9/SparcV9_Reg.td
Normal file
23
lib/Target/SparcV9/SparcV9_Reg.td
Normal file
@ -0,0 +1,23 @@
|
||||
//===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
|
||||
// vim:ft=cpp
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Declarations that describe the Sparc register file
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class V9Reg : Register { set Namespace = "SparcV9"; }
|
||||
|
||||
// Ri - One of the 32 64 bit integer registers
|
||||
class Ri<bits<5> num> : V9Reg { set Size = 64; field bits<5> Num = num; }
|
||||
|
||||
def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>;
|
||||
def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>;
|
||||
def O0 : Ri< 8>; def O1 : Ri< 9>; def O2 : Ri<10>; def O3 : Ri<11>;
|
||||
def O4 : Ri<12>; def O5 : Ri<13>; def O6 : Ri<14>; def O7 : Ri<15>;
|
||||
def L0 : Ri<16>; def L1 : Ri<17>; def L2 : Ri<18>; def L3 : Ri<19>;
|
||||
def L4 : Ri<20>; def L5 : Ri<21>; def L6 : Ri<22>; def L7 : Ri<23>;
|
||||
def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>;
|
||||
def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>;
|
||||
// Floating-point registers?
|
||||
// ...
|
||||
Loading…
Reference in New Issue
Block a user