Rewrite tblgen handling of subtarget features so

it follows the order of the enum, not alphabetical.
The motivation is to make -mattr=+ssse3,+sse41
select SSE41 as it ought to.  Added "ignored"
enum values of 0 to PPC and SPU to avoid compiler
warnings.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47143 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen
2008-02-14 23:35:16 +00:00
parent 9b03daa2a3
commit db01c8ba26
5 changed files with 10 additions and 2 deletions

View File

@ -26,6 +26,7 @@ namespace llvm {
namespace SPU { namespace SPU {
enum { enum {
PROC_NONE,
DEFAULT_PROC DEFAULT_PROC
}; };
} }

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@ -849,6 +849,7 @@ bool DarwinAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
bool DarwinAsmPrinter::doInitialization(Module &M) { bool DarwinAsmPrinter::doInitialization(Module &M) {
static const char *CPUDirectives[] = { static const char *CPUDirectives[] = {
"",
"ppc", "ppc",
"ppc601", "ppc601",
"ppc602", "ppc602",

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@ -60,6 +60,7 @@ PPCSubtarget::PPCSubtarget(const TargetMachine &tm, const Module &M,
const std::string &FS, bool is64Bit) const std::string &FS, bool is64Bit)
: TM(tm) : TM(tm)
, StackAlignment(16) , StackAlignment(16)
, DarwinDirective(PPC::DIR_NONE)
, IsGigaProcessor(false) , IsGigaProcessor(false)
, Has64BitSupport(false) , Has64BitSupport(false)
, Use64BitRegs(false) , Use64BitRegs(false)

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@ -27,6 +27,7 @@ namespace llvm {
namespace PPC { namespace PPC {
// -m directive values. // -m directive values.
enum { enum {
DIR_NONE,
DIR_32, DIR_32,
DIR_601, DIR_601,
DIR_602, DIR_602,

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@ -482,8 +482,12 @@ void SubtargetEmitter::ParseFeaturesFunction(std::ostream &OS) {
const std::string &Value = R->getValueAsString("Value"); const std::string &Value = R->getValueAsString("Value");
const std::string &Attribute = R->getValueAsString("Attribute"); const std::string &Attribute = R->getValueAsString("Attribute");
if (Value=="true" || Value=="false")
OS << " if ((Bits & " << Instance << ") != 0) " OS << " if ((Bits & " << Instance << ") != 0) "
<< Attribute << " = " << Value << ";\n"; << Attribute << " = " << Value << ";\n";
else
OS << " if ((Bits & " << Instance << ") != 0 && " << Attribute <<
" < " << Value << ") " << Attribute << " = " << Value << ";\n";
} }
if (HasItineraries) { if (HasItineraries) {