mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-25 00:29:20 +00:00
Sink feature IsThumb into MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134608 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
347c50a293
commit
db068738e8
@ -16,6 +16,12 @@
|
||||
|
||||
include "llvm/Target/Target.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// ARM Subtarget state.
|
||||
//
|
||||
|
||||
def ModeThumb : SubtargetFeature<"thumb", "IsThumb", "true",
|
||||
"Thumb mode">;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// ARM Subtarget features.
|
||||
@ -85,23 +91,23 @@ def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
|
||||
def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
|
||||
"Supports Multiprocessing extension">;
|
||||
|
||||
// ARM architectures.
|
||||
// ARM ISAs.
|
||||
def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
|
||||
"ARM v4T">;
|
||||
"Support ARM v4T instructions">;
|
||||
def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
|
||||
"ARM v5T",
|
||||
"Support ARM v5T instructions",
|
||||
[HasV4TOps]>;
|
||||
def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
|
||||
"ARM v5TE, v5TEj, v5TExp",
|
||||
"Support ARM v5TE, v5TEj, and v5TExp instructions",
|
||||
[HasV5TOps]>;
|
||||
def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
|
||||
"ARM v6",
|
||||
"Support ARM v6 instructions",
|
||||
[HasV5TEOps]>;
|
||||
def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
|
||||
"ARM v6t2",
|
||||
"Support ARM v6t2 instructions",
|
||||
[HasV6Ops, FeatureThumb2, FeatureDSPThumb2]>;
|
||||
def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
|
||||
"ARM v7",
|
||||
"Support ARM v7 instructions",
|
||||
[HasV6T2Ops]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -111,8 +117,6 @@ def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
|
||||
include "ARMSchedule.td"
|
||||
|
||||
// ARM processor families.
|
||||
def ProcOthers : SubtargetFeature<"others", "ARMProcFamily", "Others",
|
||||
"One of the other ARM processor families">;
|
||||
def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
|
||||
"Cortex-A8 ARM processors",
|
||||
[FeatureSlowFPBrcc, FeatureNEONForFP,
|
||||
|
@ -81,14 +81,13 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
|
||||
// Insert the architecture feature derived from the target triple into the
|
||||
// feature string. This is important for setting features that are implied
|
||||
// based on the architecture version.
|
||||
std::string ArchFS = ARM_MC::ParseARMTriple(TT, IsThumb);
|
||||
std::string ArchFS = ARM_MC::ParseARMTriple(TT);
|
||||
if (!FS.empty()) {
|
||||
if (!ArchFS.empty())
|
||||
ArchFS = ArchFS + "," + FS;
|
||||
else
|
||||
ArchFS = FS;
|
||||
}
|
||||
|
||||
ParseSubtargetFeatures(CPUString, ArchFS);
|
||||
|
||||
// Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
|
||||
|
@ -42,8 +42,16 @@ MCRegisterInfo *createARMMCRegisterInfo() {
|
||||
|
||||
MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
|
||||
StringRef FS) {
|
||||
std::string ArchFS = ARM_MC::ParseARMTriple(TT);
|
||||
if (!FS.empty()) {
|
||||
if (!ArchFS.empty())
|
||||
ArchFS = ArchFS + "," + FS.str();
|
||||
else
|
||||
ArchFS = FS;
|
||||
}
|
||||
|
||||
MCSubtargetInfo *X = new MCSubtargetInfo();
|
||||
InitARMMCSubtargetInfo(X, CPU, FS);
|
||||
InitARMMCSubtargetInfo(X, CPU, ArchFS);
|
||||
return X;
|
||||
}
|
||||
|
||||
@ -74,16 +82,17 @@ extern "C" void LLVMInitializeARMMCSubtargetInfo() {
|
||||
createARMMCSubtargetInfo);
|
||||
}
|
||||
|
||||
std::string ARM_MC::ParseARMTriple(StringRef TT, bool &IsThumb) {
|
||||
std::string ARM_MC::ParseARMTriple(StringRef TT) {
|
||||
// Set the boolean corresponding to the current target triple, or the default
|
||||
// if one cannot be determined, to true.
|
||||
unsigned Len = TT.size();
|
||||
unsigned Idx = 0;
|
||||
|
||||
bool isThumb = false;
|
||||
if (Len >= 5 && TT.substr(0, 4) == "armv")
|
||||
Idx = 4;
|
||||
else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
|
||||
IsThumb = true;
|
||||
isThumb = true;
|
||||
if (Len >= 7 && TT[5] == 'v')
|
||||
Idx = 6;
|
||||
}
|
||||
@ -116,5 +125,12 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, bool &IsThumb) {
|
||||
ARMArchFeature = "+v4t";
|
||||
}
|
||||
|
||||
if (isThumb) {
|
||||
if (ARMArchFeature.empty())
|
||||
ARMArchFeature = "+thumb";
|
||||
else
|
||||
ARMArchFeature += ",+thumb";
|
||||
}
|
||||
|
||||
return ARMArchFeature;
|
||||
}
|
||||
|
@ -23,7 +23,7 @@ class StringRef;
|
||||
extern Target TheARMTarget, TheThumbTarget;
|
||||
|
||||
namespace ARM_MC {
|
||||
std::string ParseARMTriple(StringRef TT, bool &IsThumb);
|
||||
std::string ParseARMTriple(StringRef TT);
|
||||
}
|
||||
|
||||
} // End llvm namespace
|
||||
|
Loading…
Reference in New Issue
Block a user