Teach regular and fast isel to set dead flags on unused implicit defs

on calls and similar instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106353 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2010-06-18 23:28:01 +00:00
parent 8af5ed9e15
commit db4971259c
7 changed files with 69 additions and 0 deletions

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@ -36,6 +36,7 @@ class TargetInstrInfo;
class TargetLowering;
class TargetMachine;
class TargetRegisterClass;
class TargetRegisterInfo;
/// FastISel - This is a fast-path instruction selection class that
/// generates poor code and doesn't support illegal types or non-trivial
@ -60,6 +61,7 @@ protected:
const TargetData &TD;
const TargetInstrInfo &TII;
const TargetLowering &TLI;
const TargetRegisterInfo &TRI;
bool IsBottomUp;
public:

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@ -364,6 +364,11 @@ public:
void addRegisterDefined(unsigned IncomingReg,
const TargetRegisterInfo *RegInfo = 0);
/// setPhysRegsDeadExcept - Mark every physreg used by this instruction as dead
/// except those in the UsedRegs list.
void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
const TargetRegisterInfo &TRI);
/// isSafeToMove - Return true if it is safe to move this instruction. If
/// SawStore is set to true, it means that there is a store (or call) between
/// the instruction's location and its intended destination.

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@ -549,6 +549,15 @@ public:
return FoundNode;
}
/// getFlaggedUser - If this node has a flag value with a user, return
/// the user (there is at most one). Otherwise return NULL.
SDNode *getFlaggedUser() const {
for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI)
if (UI.getUse().get().getValueType() == MVT::Flag)
return *UI;
return 0;
}
/// getNumValues - Return the number of values defined/returned by this
/// operator.
///

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@ -1461,6 +1461,25 @@ void MachineInstr::addRegisterDefined(unsigned IncomingReg,
true /*IsImp*/));
}
void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
const TargetRegisterInfo &TRI) {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
MachineOperand &MO = getOperand(i);
if (!MO.isReg() || !MO.isDef()) continue;
unsigned Reg = MO.getReg();
if (Reg == 0) continue;
bool Dead = true;
for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
E = UsedRegs.end(); I != E; ++I)
if (TRI.regsOverlap(*I, Reg)) {
Dead = false;
break;
}
// If there are no uses, including partial uses, the def is dead.
if (Dead) MO.setIsDead();
}
}
unsigned
MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
unsigned Hash = MI->getOpcode() * 37;

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@ -849,6 +849,7 @@ FastISel::FastISel(MachineFunction &mf,
TD(*TM.getTargetData()),
TII(*TM.getInstrInfo()),
TLI(*TM.getTargetLowering()),
TRI(*TM.getRegisterInfo()),
IsBottomUp(false) {
}

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@ -676,6 +676,33 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
// Create the new machine instruction.
MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
// The MachineInstr constructor adds implicit-def operands. Scan through
// these to determine which are dead.
if (MI->getNumOperands() != 0 &&
Node->getValueType(Node->getNumValues()-1) == MVT::Flag) {
// First, collect all used registers.
SmallVector<unsigned, 8> UsedRegs;
for (SDNode *F = Node->getFlaggedUser(); F; F = F->getFlaggedUser())
if (F->getOpcode() == ISD::CopyFromReg)
UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
else {
// Collect declared implicit uses.
const TargetInstrDesc &TID = TII->get(F->getMachineOpcode());
UsedRegs.append(TID.getImplicitUses(),
TID.getImplicitUses() + TID.getNumImplicitUses());
// In addition to declared implicit uses, we must also check for
// direct RegisterSDNode operands.
for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
unsigned Reg = R->getReg();
if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg))
UsedRegs.push_back(Reg);
}
}
// Then mark unused registers as dead.
MI->setPhysRegsDeadExcept(UsedRegs, *TRI);
}
// Add result register values for things that are defined by this
// instruction.

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@ -1555,6 +1555,7 @@ bool X86FastISel::X86SelectCall(const Instruction *I) {
BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
// Now handle call return value (if any).
SmallVector<unsigned, 4> UsedRegs;
if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext());
@ -1582,6 +1583,8 @@ bool X86FastISel::X86SelectCall(const Instruction *I) {
RVLocs[0].getLocReg(), DstRC, SrcRC, DL);
assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
Emitted = true;
UsedRegs.push_back(RVLocs[0].getLocReg());
if (CopyVT != RVLocs[0].getValVT()) {
// Round the F80 the right size, which also moves to the appropriate xmm
// register. This is accomplished by storing the F80 value in memory and
@ -1609,6 +1612,9 @@ bool X86FastISel::X86SelectCall(const Instruction *I) {
UpdateValueMap(I, ResultReg);
}
// Set all unused physreg defs as dead.
static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
return true;
}