diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index dbc04b01e20..442847cda8e 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -2305,6 +2305,16 @@ def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
                                  MOVL_shuffle_mask)))]>;
 }
 
+// Handle the v2f64 form of 'MOVZQI2PQIrr' for PR2108.  FIXME: this would be
+// better written as a dag combine xform.
+let AddedComplexity = 15 in
+def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc,
+                                  (v2f64 (scalar_to_vector 
+                                       (f64 (bitconvert GR64:$src)))),
+                                  MOVL_shuffle_mask)),
+          (MOVZQI2PQIrr GR64:$src)>, Requires<[HasSSE3]>;
+          
+
 let AddedComplexity = 20 in {
 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
                        "movd\t{$src, $dst|$dst, $src}",
diff --git a/test/CodeGen/X86/vec_shuffle-17.ll b/test/CodeGen/X86/vec_shuffle-17.ll
new file mode 100644
index 00000000000..992d79184b8
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-17.ll
@@ -0,0 +1,13 @@
+; RUN: llvm-as < %s | llc -march=x86-64 | grep {movd.*%rdi, %xmm0}
+; RUN: llvm-as < %s | llc -march=x86-64 | not grep xor
+; PR2108
+
+define <2 x i64> @doload64(i64 %x) nounwind  {
+entry:
+	%tmp717 = bitcast i64 %x to double		; <double> [#uses=1]
+	%tmp8 = insertelement <2 x double> undef, double %tmp717, i32 0		; <<2 x double>> [#uses=1]
+	%tmp9 = insertelement <2 x double> %tmp8, double 0.000000e+00, i32 1		; <<2 x double>> [#uses=1]
+	%tmp11 = bitcast <2 x double> %tmp9 to <2 x i64>		; <<2 x i64>> [#uses=1]
+	ret <2 x i64> %tmp11
+}
+