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MC: Modernize MCOperand API naming. NFC.

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MCOperand::Create*() methods renamed to MCOperand::create*().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237275 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2015-05-13 18:37:00 +00:00
parent 428e9d7608
commit db703aaedd
55 changed files with 1190 additions and 1191 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+11 -11
View File
@@ -120,11 +120,11 @@ private:
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
// Add as immediates when possible. Null MCExpr = 0.
if (!Expr)
Inst.addOperand(MCOperand::CreateImm(0));
Inst.addOperand(MCOperand::createImm(0));
else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
Inst.addOperand(MCOperand::CreateExpr(Expr));
Inst.addOperand(MCOperand::createExpr(Expr));
}
public:
@@ -253,9 +253,9 @@ public:
void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands");
assert(isMem(BDVMem) && "Invalid operand type");
Inst.addOperand(MCOperand::CreateReg(Mem.Base));
Inst.addOperand(MCOperand::createReg(Mem.Base));
addExpr(Inst, Mem.Disp);
Inst.addOperand(MCOperand::CreateReg(Mem.Index));
Inst.addOperand(MCOperand::createReg(Mem.Index));
}
// Override MCParsedAsmOperand.
@@ -267,12 +267,12 @@ public:
// to an instruction.
void addRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands");
Inst.addOperand(MCOperand::CreateReg(getReg()));
Inst.addOperand(MCOperand::createReg(getReg()));
}
void addAccessRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands");
assert(Kind == KindAccessReg && "Invalid operand type");
Inst.addOperand(MCOperand::CreateImm(AccessReg));
Inst.addOperand(MCOperand::createImm(AccessReg));
}
void addImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands");
@@ -281,20 +281,20 @@ public:
void addBDAddrOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands");
assert(isMem(BDMem) && "Invalid operand type");
Inst.addOperand(MCOperand::CreateReg(Mem.Base));
Inst.addOperand(MCOperand::createReg(Mem.Base));
addExpr(Inst, Mem.Disp);
}
void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands");
assert(isMem(BDXMem) && "Invalid operand type");
Inst.addOperand(MCOperand::CreateReg(Mem.Base));
Inst.addOperand(MCOperand::createReg(Mem.Base));
addExpr(Inst, Mem.Disp);
Inst.addOperand(MCOperand::CreateReg(Mem.Index));
Inst.addOperand(MCOperand::createReg(Mem.Index));
}
void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands");
assert(isMem(BDLMem) && "Invalid operand type");
Inst.addOperand(MCOperand::CreateReg(Mem.Base));
Inst.addOperand(MCOperand::createReg(Mem.Base));
addExpr(Inst, Mem.Disp);
addExpr(Inst, Mem.Length);
}
lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
+20 -20
View File
@@ -52,7 +52,7 @@ static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
RegNo = Regs[RegNo];
if (RegNo == 0)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateReg(RegNo));
Inst.addOperand(MCOperand::createReg(RegNo));
return MCDisassembler::Success;
}
@@ -126,7 +126,7 @@ template<unsigned N>
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
if (!isUInt<N>(Imm))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Imm));
Inst.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -134,7 +134,7 @@ template<unsigned N>
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
if (!isUInt<N>(Imm))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm)));
Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
return MCDisassembler::Success;
}
@@ -208,7 +208,7 @@ template<unsigned N>
static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm,
uint64_t Address) {
assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm) * 2 + Address));
Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm) * 2 + Address));
return MCDisassembler::Success;
}
@@ -229,8 +229,8 @@ static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field,
uint64_t Base = Field >> 12;
uint64_t Disp = Field & 0xfff;
assert(Base < 16 && "Invalid BDAddr12");
Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::CreateImm(Disp));
Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::createImm(Disp));
return MCDisassembler::Success;
}
@@ -239,8 +239,8 @@ static DecodeStatus decodeBDAddr20Operand(MCInst &Inst, uint64_t Field,
uint64_t Base = Field >> 20;
uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
assert(Base < 16 && "Invalid BDAddr20");
Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp)));
Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
return MCDisassembler::Success;
}
@@ -250,9 +250,9 @@ static DecodeStatus decodeBDXAddr12Operand(MCInst &Inst, uint64_t Field,
uint64_t Base = (Field >> 12) & 0xf;
uint64_t Disp = Field & 0xfff;
assert(Index < 16 && "Invalid BDXAddr12");
Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::CreateImm(Disp));
Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index]));
Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::createImm(Disp));
Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
return MCDisassembler::Success;
}
@@ -262,9 +262,9 @@ static DecodeStatus decodeBDXAddr20Operand(MCInst &Inst, uint64_t Field,
uint64_t Base = (Field >> 20) & 0xf;
uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
assert(Index < 16 && "Invalid BDXAddr20");
Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp)));
Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index]));
Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
return MCDisassembler::Success;
}
@@ -274,9 +274,9 @@ static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field,
uint64_t Base = (Field >> 12) & 0xf;
uint64_t Disp = Field & 0xfff;
assert(Length < 256 && "Invalid BDLAddr12Len8");
Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::CreateImm(Disp));
Inst.addOperand(MCOperand::CreateImm(Length + 1));
Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::createImm(Disp));
Inst.addOperand(MCOperand::createImm(Length + 1));
return MCDisassembler::Success;
}
@@ -286,9 +286,9 @@ static DecodeStatus decodeBDVAddr12Operand(MCInst &Inst, uint64_t Field,
uint64_t Base = (Field >> 12) & 0xf;
uint64_t Disp = Field & 0xfff;
assert(Index < 32 && "Invalid BDVAddr12");
Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::CreateImm(Disp));
Inst.addOperand(MCOperand::CreateReg(SystemZMC::VR128Regs[Index]));
Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
Inst.addOperand(MCOperand::createImm(Disp));
Inst.addOperand(MCOperand::createReg(SystemZMC::VR128Regs[Index]));
return MCDisassembler::Success;
}
lib/Target/SystemZ/SystemZMCInstLower.cpp
+3 -3
View File
@@ -79,14 +79,14 @@ SystemZMCInstLower::getExpr(const MachineOperand &MO,
MCOperand SystemZMCInstLower::lowerOperand(const MachineOperand &MO) const {
switch (MO.getType()) {
case MachineOperand::MO_Register:
return MCOperand::CreateReg(MO.getReg());
return MCOperand::createReg(MO.getReg());
case MachineOperand::MO_Immediate:
return MCOperand::CreateImm(MO.getImm());
return MCOperand::createImm(MO.getImm());
default: {
MCSymbolRefExpr::VariantKind Kind = getVariantKind(MO.getTargetFlags());
return MCOperand::CreateExpr(getExpr(MO, Kind));
return MCOperand::createExpr(getExpr(MO, Kind));
}
}
}